^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/arm/common/sa1111.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * SA1111 support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Original code by John Dorsey
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * This file contains all generic SA1111 support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * All initialization functions provided here are intended to be called
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * from machine specific code with proper arguments when required.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/dma-map-ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <mach/hardware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <asm/mach/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <asm/hardware/sa1111.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* SA1111 IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define IRQ_GPAIN0 (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define IRQ_GPAIN1 (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define IRQ_GPAIN2 (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define IRQ_GPAIN3 (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define IRQ_GPBIN0 (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define IRQ_GPBIN1 (5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define IRQ_GPBIN2 (6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define IRQ_GPBIN3 (7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define IRQ_GPBIN4 (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define IRQ_GPBIN5 (9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define IRQ_GPCIN0 (10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define IRQ_GPCIN1 (11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define IRQ_GPCIN2 (12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define IRQ_GPCIN3 (13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define IRQ_GPCIN4 (14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define IRQ_GPCIN5 (15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define IRQ_GPCIN6 (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define IRQ_GPCIN7 (17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define IRQ_MSTXINT (18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define IRQ_MSRXINT (19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define IRQ_MSSTOPERRINT (20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define IRQ_TPTXINT (21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define IRQ_TPRXINT (22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define IRQ_TPSTOPERRINT (23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SSPXMTINT (24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SSPRCVINT (25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SSPROR (26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define AUDXMTDMADONEA (32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define AUDRCVDMADONEA (33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define AUDXMTDMADONEB (34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define AUDRCVDMADONEB (35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define AUDTFSR (36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define AUDRFSR (37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define AUDTUR (38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define AUDROR (39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define AUDDTS (40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define AUDRDD (41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define AUDSTO (42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define IRQ_USBPWR (43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define IRQ_HCIM (44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define IRQ_HCIBUFFACC (45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define IRQ_HCIRMTWKP (46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define IRQ_NHCIMFCIR (47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define IRQ_USB_PORT_RESUME (48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define IRQ_S0_READY_NINT (49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define IRQ_S1_READY_NINT (50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define IRQ_S0_CD_VALID (51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define IRQ_S1_CD_VALID (52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define IRQ_S0_BVD1_STSCHG (53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define IRQ_S1_BVD1_STSCHG (54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SA1111_IRQ_NR (55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) extern void sa1110_mb_enable(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) extern void sa1110_mb_disable(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * We keep the following data for the overall SA1111. Note that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * struct device and struct resource are "fake"; they should be supplied
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * by the bus above us. However, in the interests of getting all SA1111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * drivers converted over to the device model, we provide this as an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * anchor point for all the other drivers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct sa1111 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) unsigned long phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) int irq_base; /* base for cascaded on-chip IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct sa1111_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct irq_domain *irqdomain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct gpio_chip gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) void *saved_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * We _really_ need to eliminate this. Its only users
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * are the PWM and DMA checking code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static struct sa1111 *g_sa1111;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct sa1111_dev_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned long offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) unsigned long skpcr_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) bool dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) unsigned int devid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) unsigned int hwirq[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static struct sa1111_dev_info sa1111_devices[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .offset = SA1111_USB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .skpcr_mask = SKPCR_UCLKEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .dma = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .devid = SA1111_DEVID_USB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .hwirq = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) IRQ_USBPWR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) IRQ_HCIM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) IRQ_HCIBUFFACC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) IRQ_HCIRMTWKP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) IRQ_NHCIMFCIR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) IRQ_USB_PORT_RESUME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .offset = 0x0600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .skpcr_mask = SKPCR_I2SCLKEN | SKPCR_L3CLKEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .dma = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .devid = SA1111_DEVID_SAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .hwirq = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) AUDXMTDMADONEA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) AUDXMTDMADONEB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) AUDRCVDMADONEA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) AUDRCVDMADONEB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .offset = 0x0800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .skpcr_mask = SKPCR_SCLKEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .devid = SA1111_DEVID_SSP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .offset = SA1111_KBD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .skpcr_mask = SKPCR_PTCLKEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .devid = SA1111_DEVID_PS2_KBD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .hwirq = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) IRQ_TPRXINT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) IRQ_TPTXINT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .offset = SA1111_MSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .skpcr_mask = SKPCR_PMCLKEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .devid = SA1111_DEVID_PS2_MSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .hwirq = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) IRQ_MSRXINT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) IRQ_MSTXINT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .offset = 0x1800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .skpcr_mask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .devid = SA1111_DEVID_PCMCIA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .hwirq = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) IRQ_S0_READY_NINT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) IRQ_S0_CD_VALID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) IRQ_S0_BVD1_STSCHG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) IRQ_S1_READY_NINT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) IRQ_S1_CD_VALID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) IRQ_S1_BVD1_STSCHG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static int sa1111_map_irq(struct sa1111 *sachip, irq_hw_number_t hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return irq_create_mapping(sachip->irqdomain, hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static void sa1111_handle_irqdomain(struct irq_domain *irqdomain, int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct irq_desc *d = irq_to_desc(irq_linear_revmap(irqdomain, irq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) generic_handle_irq_desc(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * SA1111 interrupt support. Since clearing an IRQ while there are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * active IRQs causes the interrupt output to pulse, the upper levels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * will call us again if there are more interrupts to process.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static void sa1111_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) unsigned int stat0, stat1, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct sa1111 *sachip = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct irq_domain *irqdomain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) void __iomem *mapbase = sachip->base + SA1111_INTC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) stat0 = readl_relaxed(mapbase + SA1111_INTSTATCLR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) stat1 = readl_relaxed(mapbase + SA1111_INTSTATCLR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) writel_relaxed(stat0, mapbase + SA1111_INTSTATCLR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) desc->irq_data.chip->irq_ack(&desc->irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) writel_relaxed(stat1, mapbase + SA1111_INTSTATCLR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (stat0 == 0 && stat1 == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) do_bad_IRQ(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) irqdomain = sachip->irqdomain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) for (i = 0; stat0; i++, stat0 >>= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (stat0 & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) sa1111_handle_irqdomain(irqdomain, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) for (i = 32; stat1; i++, stat1 >>= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (stat1 & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) sa1111_handle_irqdomain(irqdomain, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* For level-based interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) desc->irq_data.chip->irq_unmask(&desc->irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static u32 sa1111_irqmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return BIT(irqd_to_hwirq(d) & 31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static int sa1111_irqbank(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return (irqd_to_hwirq(d) / 32) * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static void sa1111_ack_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static void sa1111_mask_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) u32 ie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) ie = readl_relaxed(mapbase + SA1111_INTEN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) ie &= ~sa1111_irqmask(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) writel(ie, mapbase + SA1111_INTEN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static void sa1111_unmask_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) u32 ie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) ie = readl_relaxed(mapbase + SA1111_INTEN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) ie |= sa1111_irqmask(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) writel_relaxed(ie, mapbase + SA1111_INTEN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * Attempt to re-trigger the interrupt. The SA1111 contains a register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * (INTSET) which claims to do this. However, in practice no amount of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * manipulation of INTEN and INTSET guarantees that the interrupt will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * be triggered. In fact, its very difficult, if not impossible to get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * INTSET to re-trigger the interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static int sa1111_retrigger_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) u32 ip, mask = sa1111_irqmask(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) ip = readl_relaxed(mapbase + SA1111_INTPOL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) for (i = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) writel_relaxed(ip ^ mask, mapbase + SA1111_INTPOL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) writel_relaxed(ip, mapbase + SA1111_INTPOL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (readl_relaxed(mapbase + SA1111_INTSTATCLR0) & mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (i == 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) pr_err("Danger Will Robinson: failed to re-trigger IRQ%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) d->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static int sa1111_type_irq(struct irq_data *d, unsigned int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) u32 ip, mask = sa1111_irqmask(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (flags == IRQ_TYPE_PROBE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if ((!(flags & IRQ_TYPE_EDGE_RISING) ^ !(flags & IRQ_TYPE_EDGE_FALLING)) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ip = readl_relaxed(mapbase + SA1111_INTPOL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (flags & IRQ_TYPE_EDGE_RISING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) ip &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) ip |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) writel_relaxed(ip, mapbase + SA1111_INTPOL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) writel_relaxed(ip, mapbase + SA1111_WAKEPOL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static int sa1111_wake_irq(struct irq_data *d, unsigned int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) u32 we, mask = sa1111_irqmask(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) we = readl_relaxed(mapbase + SA1111_WAKEEN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) we |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) we &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) writel_relaxed(we, mapbase + SA1111_WAKEEN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static struct irq_chip sa1111_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .name = "SA1111",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .irq_ack = sa1111_ack_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .irq_mask = sa1111_mask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .irq_unmask = sa1111_unmask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .irq_retrigger = sa1111_retrigger_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .irq_set_type = sa1111_type_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .irq_set_wake = sa1111_wake_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static int sa1111_irqdomain_map(struct irq_domain *d, unsigned int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) irq_hw_number_t hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) struct sa1111 *sachip = d->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* Disallow unavailable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (hwirq > SSPROR && hwirq < AUDXMTDMADONEA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) irq_set_chip_data(irq, sachip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) irq_set_chip_and_handler(irq, &sa1111_irq_chip, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static const struct irq_domain_ops sa1111_irqdomain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .map = sa1111_irqdomain_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .xlate = irq_domain_xlate_twocell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static int sa1111_setup_irq(struct sa1111 *sachip, unsigned irq_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) void __iomem *irqbase = sachip->base + SA1111_INTC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * We're guaranteed that this region hasn't been taken.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) request_mem_region(sachip->phys + SA1111_INTC, 512, "irq");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ret = irq_alloc_descs(-1, irq_base, SA1111_IRQ_NR, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (ret <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) dev_err(sachip->dev, "unable to allocate %u irqs: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) SA1111_IRQ_NR, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) sachip->irq_base = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* disable all IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) writel_relaxed(0, irqbase + SA1111_INTEN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) writel_relaxed(0, irqbase + SA1111_INTEN1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) writel_relaxed(0, irqbase + SA1111_WAKEEN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) writel_relaxed(0, irqbase + SA1111_WAKEEN1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * detect on rising edge. Note: Feb 2001 Errata for SA1111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * specifies that S0ReadyInt and S1ReadyInt should be '1'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) writel_relaxed(0, irqbase + SA1111_INTPOL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) writel_relaxed(BIT(IRQ_S0_READY_NINT & 31) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) BIT(IRQ_S1_READY_NINT & 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) irqbase + SA1111_INTPOL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* clear all IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) writel_relaxed(~0, irqbase + SA1111_INTSTATCLR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) writel_relaxed(~0, irqbase + SA1111_INTSTATCLR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) sachip->irqdomain = irq_domain_add_linear(NULL, SA1111_IRQ_NR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) &sa1111_irqdomain_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) sachip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (!sachip->irqdomain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) irq_free_descs(sachip->irq_base, SA1111_IRQ_NR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) irq_domain_associate_many(sachip->irqdomain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) sachip->irq_base + IRQ_GPAIN0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) IRQ_GPAIN0, SSPROR + 1 - IRQ_GPAIN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) irq_domain_associate_many(sachip->irqdomain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) sachip->irq_base + AUDXMTDMADONEA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) AUDXMTDMADONEA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) IRQ_S1_BVD1_STSCHG + 1 - AUDXMTDMADONEA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * Register SA1111 interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) irq_set_irq_type(sachip->irq, IRQ_TYPE_EDGE_RISING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) irq_set_chained_handler_and_data(sachip->irq, sa1111_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) sachip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) dev_info(sachip->dev, "Providing IRQ%u-%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) sachip->irq_base, sachip->irq_base + SA1111_IRQ_NR - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static void sa1111_remove_irq(struct sa1111 *sachip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct irq_domain *domain = sachip->irqdomain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) void __iomem *irqbase = sachip->base + SA1111_INTC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /* disable all IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) writel_relaxed(0, irqbase + SA1111_INTEN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) writel_relaxed(0, irqbase + SA1111_INTEN1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) writel_relaxed(0, irqbase + SA1111_WAKEEN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) writel_relaxed(0, irqbase + SA1111_WAKEEN1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) irq_set_chained_handler_and_data(sachip->irq, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) for (i = 0; i < SA1111_IRQ_NR; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) irq_dispose_mapping(irq_find_mapping(domain, i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) irq_domain_remove(domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) release_mem_region(sachip->phys + SA1111_INTC, 512);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) SA1111_GPIO_PXDDR = (SA1111_GPIO_PADDR - SA1111_GPIO_PADDR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) SA1111_GPIO_PXDRR = (SA1111_GPIO_PADRR - SA1111_GPIO_PADDR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) SA1111_GPIO_PXDWR = (SA1111_GPIO_PADWR - SA1111_GPIO_PADDR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) SA1111_GPIO_PXSDR = (SA1111_GPIO_PASDR - SA1111_GPIO_PADDR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) SA1111_GPIO_PXSSR = (SA1111_GPIO_PASSR - SA1111_GPIO_PADDR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static struct sa1111 *gc_to_sa1111(struct gpio_chip *gc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return container_of(gc, struct sa1111, gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static void __iomem *sa1111_gpio_map_reg(struct sa1111 *sachip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) void __iomem *reg = sachip->base + SA1111_GPIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (offset < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) return reg + SA1111_GPIO_PADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (offset < 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return reg + SA1111_GPIO_PBDDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (offset < 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return reg + SA1111_GPIO_PCDDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static u32 sa1111_gpio_map_bit(unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (offset < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (offset < 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return BIT(offset - 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (offset < 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return BIT(offset - 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static void sa1111_gpio_modify(void __iomem *reg, u32 mask, u32 set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) val = readl_relaxed(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) val &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) val |= mask & set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) writel_relaxed(val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static int sa1111_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) struct sa1111 *sachip = gc_to_sa1111(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) void __iomem *reg = sa1111_gpio_map_reg(sachip, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) u32 mask = sa1111_gpio_map_bit(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return !!(readl_relaxed(reg + SA1111_GPIO_PXDDR) & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) static int sa1111_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct sa1111 *sachip = gc_to_sa1111(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) void __iomem *reg = sa1111_gpio_map_reg(sachip, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) u32 mask = sa1111_gpio_map_bit(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) spin_lock_irqsave(&sachip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) sa1111_gpio_modify(reg + SA1111_GPIO_PXDDR, mask, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) sa1111_gpio_modify(reg + SA1111_GPIO_PXSDR, mask, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) spin_unlock_irqrestore(&sachip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static int sa1111_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) struct sa1111 *sachip = gc_to_sa1111(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) void __iomem *reg = sa1111_gpio_map_reg(sachip, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) u32 mask = sa1111_gpio_map_bit(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) spin_lock_irqsave(&sachip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) sa1111_gpio_modify(reg + SA1111_GPIO_PXDWR, mask, value ? mask : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) sa1111_gpio_modify(reg + SA1111_GPIO_PXSSR, mask, value ? mask : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) sa1111_gpio_modify(reg + SA1111_GPIO_PXDDR, mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) sa1111_gpio_modify(reg + SA1111_GPIO_PXSDR, mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) spin_unlock_irqrestore(&sachip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static int sa1111_gpio_get(struct gpio_chip *gc, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) struct sa1111 *sachip = gc_to_sa1111(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) void __iomem *reg = sa1111_gpio_map_reg(sachip, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) u32 mask = sa1111_gpio_map_bit(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) return !!(readl_relaxed(reg + SA1111_GPIO_PXDRR) & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) static void sa1111_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) struct sa1111 *sachip = gc_to_sa1111(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) void __iomem *reg = sa1111_gpio_map_reg(sachip, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) u32 mask = sa1111_gpio_map_bit(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) spin_lock_irqsave(&sachip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) sa1111_gpio_modify(reg + SA1111_GPIO_PXDWR, mask, value ? mask : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) sa1111_gpio_modify(reg + SA1111_GPIO_PXSSR, mask, value ? mask : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) spin_unlock_irqrestore(&sachip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static void sa1111_gpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) unsigned long *bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) struct sa1111 *sachip = gc_to_sa1111(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) void __iomem *reg = sachip->base + SA1111_GPIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) u32 msk, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) msk = *mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) val = *bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) spin_lock_irqsave(&sachip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) sa1111_gpio_modify(reg + SA1111_GPIO_PADWR, msk & 15, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) sa1111_gpio_modify(reg + SA1111_GPIO_PASSR, msk & 15, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) sa1111_gpio_modify(reg + SA1111_GPIO_PBDWR, (msk >> 4) & 255, val >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) sa1111_gpio_modify(reg + SA1111_GPIO_PBSSR, (msk >> 4) & 255, val >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) sa1111_gpio_modify(reg + SA1111_GPIO_PCDWR, (msk >> 12) & 255, val >> 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) sa1111_gpio_modify(reg + SA1111_GPIO_PCSSR, (msk >> 12) & 255, val >> 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) spin_unlock_irqrestore(&sachip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static int sa1111_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) struct sa1111 *sachip = gc_to_sa1111(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) return sa1111_map_irq(sachip, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static int sa1111_setup_gpios(struct sa1111 *sachip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) sachip->gc.label = "sa1111";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) sachip->gc.parent = sachip->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) sachip->gc.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) sachip->gc.get_direction = sa1111_gpio_get_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) sachip->gc.direction_input = sa1111_gpio_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) sachip->gc.direction_output = sa1111_gpio_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) sachip->gc.get = sa1111_gpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) sachip->gc.set = sa1111_gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) sachip->gc.set_multiple = sa1111_gpio_set_multiple;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) sachip->gc.to_irq = sa1111_gpio_to_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) sachip->gc.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) sachip->gc.ngpio = 18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return devm_gpiochip_add_data(sachip->dev, &sachip->gc, sachip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) * Bring the SA1111 out of reset. This requires a set procedure:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) * 1. nRESET asserted (by hardware)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) * 2. CLK turned on from SA1110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) * 3. nRESET deasserted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) * 4. VCO turned on, PLL_BYPASS turned off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * 5. Wait lock time, then assert RCLKEn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) * 7. PCR set to allow clocking of individual functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * Until we've done this, the only registers we can access are:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * SBI_SKCR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * SBI_SMCR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * SBI_SKID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) static void sa1111_wake(struct sa1111 *sachip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) unsigned long flags, r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) spin_lock_irqsave(&sachip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) clk_enable(sachip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) * Turn VCO on, and disable PLL Bypass.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) r = readl_relaxed(sachip->base + SA1111_SKCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) r &= ~SKCR_VCO_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) writel_relaxed(r, sachip->base + SA1111_SKCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) r |= SKCR_PLL_BYPASS | SKCR_OE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) writel_relaxed(r, sachip->base + SA1111_SKCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) * Wait lock time. SA1111 manual _doesn't_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) * specify a figure for this! We choose 100us.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * Enable RCLK. We also ensure that RDYEN is set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) r |= SKCR_RCLKEN | SKCR_RDYEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) writel_relaxed(r, sachip->base + SA1111_SKCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) * Wait 14 RCLK cycles for the chip to finish coming out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) * of reset. (RCLK=24MHz). This is 590ns.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) * Ensure all clocks are initially off.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) writel_relaxed(0, sachip->base + SA1111_SKPCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) spin_unlock_irqrestore(&sachip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #ifdef CONFIG_ARCH_SA1100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) static u32 sa1111_dma_mask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) ~(1 << 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) ~(1 << 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) ~(1 << 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) ~(1 << 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) ~(1 << 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) ~(1 << 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) * Configure the SA1111 shared memory controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) sa1111_configure_smc(struct sa1111 *sachip, int sdram, unsigned int drac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) unsigned int cas_latency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) unsigned int smcr = SMCR_DTIM | SMCR_MBGE | FInsrt(drac, SMCR_DRAC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) if (cas_latency == 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) smcr |= SMCR_CLAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) writel_relaxed(smcr, sachip->base + SA1111_SMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) * Now clear the bits in the DMA mask to work around the SA1111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) * DMA erratum (Intel StrongARM SA-1111 Microprocessor Companion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) * Chip Specification Update, June 2000, Erratum #7).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (sachip->dev->dma_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) *sachip->dev->dma_mask &= sa1111_dma_mask[drac >> 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) sachip->dev->coherent_dma_mask &= sa1111_dma_mask[drac >> 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) static void sa1111_dev_release(struct device *_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) struct sa1111_dev *dev = to_sa1111_device(_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) kfree(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) sa1111_init_one_child(struct sa1111 *sachip, struct resource *parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) struct sa1111_dev_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) struct sa1111_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) unsigned i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) dev = kzalloc(sizeof(struct sa1111_dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) if (!dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) goto err_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) device_initialize(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) dev_set_name(&dev->dev, "%4.4lx", info->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) dev->devid = info->devid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) dev->dev.parent = sachip->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) dev->dev.bus = &sa1111_bus_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) dev->dev.release = sa1111_dev_release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) dev->res.start = sachip->phys + info->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) dev->res.end = dev->res.start + 511;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) dev->res.name = dev_name(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) dev->res.flags = IORESOURCE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) dev->mapbase = sachip->base + info->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) dev->skpcr_mask = info->skpcr_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) for (i = 0; i < ARRAY_SIZE(info->hwirq); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) dev->hwirq[i] = info->hwirq[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) * If the parent device has a DMA mask associated with it, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) * this child supports DMA, propagate it down to the children.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if (info->dma && sachip->dev->dma_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) dev->dma_mask = *sachip->dev->dma_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) dev->dev.dma_mask = &dev->dma_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) dev->dev.coherent_dma_mask = sachip->dev->coherent_dma_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) ret = request_resource(parent, &dev->res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) dev_err(sachip->dev, "failed to allocate resource for %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) dev->res.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) goto err_resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) ret = device_add(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) goto err_add;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) err_add:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) release_resource(&dev->res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) err_resource:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) put_device(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) err_alloc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) * sa1111_probe - probe for a single SA1111 chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) * @phys_addr: physical address of device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) * Probe for a SA1111 chip. This must be called
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) * before any other SA1111-specific code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) * %-ENODEV device not found.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) * %-EBUSY physical address already marked in-use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) * %-EINVAL no platform data passed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) * %0 successful.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) static int __sa1111_probe(struct device *me, struct resource *mem, int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) struct sa1111_platform_data *pd = me->platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) struct sa1111 *sachip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) unsigned long id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) unsigned int has_devs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) int i, ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (!pd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) sachip = devm_kzalloc(me, sizeof(struct sa1111), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) if (!sachip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) sachip->clk = devm_clk_get(me, "SA1111_CLK");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if (IS_ERR(sachip->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) return PTR_ERR(sachip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) ret = clk_prepare(sachip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) spin_lock_init(&sachip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) sachip->dev = me;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) dev_set_drvdata(sachip->dev, sachip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) sachip->pdata = pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) sachip->phys = mem->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) sachip->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) * Map the whole region. This also maps the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) * registers for our children.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) sachip->base = ioremap(mem->start, PAGE_SIZE * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) if (!sachip->base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) goto err_clk_unprep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) * Probe for the chip. Only touch the SBI registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) id = readl_relaxed(sachip->base + SA1111_SKID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) if ((id & SKID_ID_MASK) != SKID_SA1111_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) printk(KERN_DEBUG "SA1111 not detected: ID = %08lx\n", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) goto err_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) pr_info("SA1111 Microprocessor Companion Chip: silicon revision %lx, metal revision %lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) (id & SKID_SIREV_MASK) >> 4, id & SKID_MTREV_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) * We found it. Wake the chip up, and initialise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) sa1111_wake(sachip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) * The interrupt controller must be initialised before any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) * other device to ensure that the interrupts are available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) ret = sa1111_setup_irq(sachip, pd->irq_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) /* Setup the GPIOs - should really be done after the IRQ setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) ret = sa1111_setup_gpios(sachip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) goto err_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) #ifdef CONFIG_ARCH_SA1100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) * The SDRAM configuration of the SA1110 and the SA1111 must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) * match. This is very important to ensure that SA1111 accesses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) * don't corrupt the SDRAM. Note that this ungates the SA1111's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) * MBGNT signal, so we must have called sa1110_mb_disable()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) * beforehand.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) sa1111_configure_smc(sachip, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) FExtr(MDCNFG, MDCNFG_SA1110_DRAC0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) FExtr(MDCNFG, MDCNFG_SA1110_TDL0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) * We only need to turn on DCLK whenever we want to use the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) * DMA. It can otherwise be held firmly in the off position.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) * (currently, we always enable it.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) val = readl_relaxed(sachip->base + SA1111_SKPCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) writel_relaxed(val | SKPCR_DCLKEN, sachip->base + SA1111_SKPCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) * Enable the SA1110 memory bus request and grant signals.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) sa1110_mb_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) g_sa1111 = sachip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) has_devs = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) if (pd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) has_devs &= ~pd->disable_devs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) for (i = 0; i < ARRAY_SIZE(sa1111_devices); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) if (sa1111_devices[i].devid & has_devs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) sa1111_init_one_child(sachip, mem, &sa1111_devices[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) err_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) sa1111_remove_irq(sachip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) err_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) clk_disable(sachip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) err_unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) iounmap(sachip->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) err_clk_unprep:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) clk_unprepare(sachip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) static int sa1111_remove_one(struct device *dev, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) struct sa1111_dev *sadev = to_sa1111_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) if (dev->bus != &sa1111_bus_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) device_del(&sadev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) release_resource(&sadev->res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) put_device(&sadev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) static void __sa1111_remove(struct sa1111 *sachip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) device_for_each_child(sachip->dev, NULL, sa1111_remove_one);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) sa1111_remove_irq(sachip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) clk_disable(sachip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) clk_unprepare(sachip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) iounmap(sachip->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) struct sa1111_save_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) unsigned int skcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) unsigned int skpcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) unsigned int skcdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) unsigned char skaud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) unsigned char skpwm0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) unsigned char skpwm1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) * Interrupt controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) unsigned int intpol0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) unsigned int intpol1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) unsigned int inten0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) unsigned int inten1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) unsigned int wakepol0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) unsigned int wakepol1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) unsigned int wakeen0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) unsigned int wakeen1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) static int sa1111_suspend_noirq(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) struct sa1111 *sachip = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) struct sa1111_save_data *save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) save = kmalloc(sizeof(struct sa1111_save_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) if (!save)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) sachip->saved_state = save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) spin_lock_irqsave(&sachip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) * Save state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) base = sachip->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) save->skcr = readl_relaxed(base + SA1111_SKCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) save->skpcr = readl_relaxed(base + SA1111_SKPCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) save->skcdr = readl_relaxed(base + SA1111_SKCDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) save->skaud = readl_relaxed(base + SA1111_SKAUD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) save->skpwm0 = readl_relaxed(base + SA1111_SKPWM0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) save->skpwm1 = readl_relaxed(base + SA1111_SKPWM1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) writel_relaxed(0, sachip->base + SA1111_SKPWM0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) writel_relaxed(0, sachip->base + SA1111_SKPWM1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) base = sachip->base + SA1111_INTC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) save->intpol0 = readl_relaxed(base + SA1111_INTPOL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) save->intpol1 = readl_relaxed(base + SA1111_INTPOL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) save->inten0 = readl_relaxed(base + SA1111_INTEN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) save->inten1 = readl_relaxed(base + SA1111_INTEN1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) save->wakepol0 = readl_relaxed(base + SA1111_WAKEPOL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) save->wakepol1 = readl_relaxed(base + SA1111_WAKEPOL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) save->wakeen0 = readl_relaxed(base + SA1111_WAKEEN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) save->wakeen1 = readl_relaxed(base + SA1111_WAKEEN1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) * Disable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) val = readl_relaxed(sachip->base + SA1111_SKCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) writel_relaxed(val | SKCR_SLEEP, sachip->base + SA1111_SKCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) clk_disable(sachip->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) spin_unlock_irqrestore(&sachip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) #ifdef CONFIG_ARCH_SA1100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) sa1110_mb_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) * sa1111_resume - Restore the SA1111 device state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) * @dev: device to restore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) * Restore the general state of the SA1111; clock control and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) * interrupt controller. Other parts of the SA1111 must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) * restored by their respective drivers, and must be called
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) * via LDM after this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) static int sa1111_resume_noirq(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) struct sa1111 *sachip = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) struct sa1111_save_data *save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) unsigned long flags, id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) save = sachip->saved_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) if (!save)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) * Ensure that the SA1111 is still here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) * FIXME: shouldn't do this here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) id = readl_relaxed(sachip->base + SA1111_SKID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) if ((id & SKID_ID_MASK) != SKID_SA1111_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) __sa1111_remove(sachip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) dev_set_drvdata(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) kfree(save);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) * First of all, wake up the chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) sa1111_wake(sachip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) #ifdef CONFIG_ARCH_SA1100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) /* Enable the memory bus request/grant signals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) sa1110_mb_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) * Only lock for write ops. Also, sa1111_wake must be called with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) * released spinlock!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) spin_lock_irqsave(&sachip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) writel_relaxed(0, sachip->base + SA1111_INTC + SA1111_INTEN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) writel_relaxed(0, sachip->base + SA1111_INTC + SA1111_INTEN1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) base = sachip->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) writel_relaxed(save->skcr, base + SA1111_SKCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) writel_relaxed(save->skpcr, base + SA1111_SKPCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) writel_relaxed(save->skcdr, base + SA1111_SKCDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) writel_relaxed(save->skaud, base + SA1111_SKAUD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) writel_relaxed(save->skpwm0, base + SA1111_SKPWM0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) writel_relaxed(save->skpwm1, base + SA1111_SKPWM1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) base = sachip->base + SA1111_INTC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) writel_relaxed(save->intpol0, base + SA1111_INTPOL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) writel_relaxed(save->intpol1, base + SA1111_INTPOL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) writel_relaxed(save->inten0, base + SA1111_INTEN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) writel_relaxed(save->inten1, base + SA1111_INTEN1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) writel_relaxed(save->wakepol0, base + SA1111_WAKEPOL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) writel_relaxed(save->wakepol1, base + SA1111_WAKEPOL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) writel_relaxed(save->wakeen0, base + SA1111_WAKEEN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) writel_relaxed(save->wakeen1, base + SA1111_WAKEEN1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) spin_unlock_irqrestore(&sachip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) sachip->saved_state = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) kfree(save);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) #define sa1111_suspend_noirq NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) #define sa1111_resume_noirq NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) static int sa1111_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) struct resource *mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) if (!mem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) return __sa1111_probe(&pdev->dev, mem, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) static int sa1111_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) struct sa1111 *sachip = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) if (sachip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) kfree(sachip->saved_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) sachip->saved_state = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) __sa1111_remove(sachip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) platform_set_drvdata(pdev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) static struct dev_pm_ops sa1111_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) .suspend_noirq = sa1111_suspend_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) .resume_noirq = sa1111_resume_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) * Not sure if this should be on the system bus or not yet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) * We really want some way to register a system device at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) * the per-machine level, and then have this driver pick
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) * up the registered devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) * We also need to handle the SDRAM configuration for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) * PXA250/SA1110 machine classes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) static struct platform_driver sa1111_device_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) .probe = sa1111_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) .remove = sa1111_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) .name = "sa1111",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) .pm = &sa1111_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) * Get the parent device driver (us) structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) * from a child function device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) static inline struct sa1111 *sa1111_chip_driver(struct sa1111_dev *sadev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) return (struct sa1111 *)dev_get_drvdata(sadev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) * The bits in the opdiv field are non-linear.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) static unsigned char opdiv_table[] = { 1, 4, 2, 8 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) static unsigned int __sa1111_pll_clock(struct sa1111 *sachip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) unsigned int skcdr, fbdiv, ipdiv, opdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) skcdr = readl_relaxed(sachip->base + SA1111_SKCDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) fbdiv = (skcdr & 0x007f) + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) ipdiv = ((skcdr & 0x0f80) >> 7) + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) opdiv = opdiv_table[(skcdr & 0x3000) >> 12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) return 3686400 * fbdiv / (ipdiv * opdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) * sa1111_pll_clock - return the current PLL clock frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) * @sadev: SA1111 function block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) * BUG: we should look at SKCR. We also blindly believe that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) * the chip is being fed with the 3.6864MHz clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) * Returns the PLL clock in Hz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) unsigned int sa1111_pll_clock(struct sa1111_dev *sadev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) struct sa1111 *sachip = sa1111_chip_driver(sadev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) return __sa1111_pll_clock(sachip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) EXPORT_SYMBOL(sa1111_pll_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) * sa1111_select_audio_mode - select I2S or AC link mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) * @sadev: SA1111 function block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) * @mode: One of %SA1111_AUDIO_ACLINK or %SA1111_AUDIO_I2S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) * Frob the SKCR to select AC Link mode or I2S mode for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) * the audio block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) void sa1111_select_audio_mode(struct sa1111_dev *sadev, int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) struct sa1111 *sachip = sa1111_chip_driver(sadev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) spin_lock_irqsave(&sachip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) val = readl_relaxed(sachip->base + SA1111_SKCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) if (mode == SA1111_AUDIO_I2S) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) val &= ~SKCR_SELAC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) val |= SKCR_SELAC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) writel_relaxed(val, sachip->base + SA1111_SKCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) spin_unlock_irqrestore(&sachip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) EXPORT_SYMBOL(sa1111_select_audio_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) * sa1111_set_audio_rate - set the audio sample rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) * @sadev: SA1111 SAC function block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) * @rate: sample rate to select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) int sa1111_set_audio_rate(struct sa1111_dev *sadev, int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) struct sa1111 *sachip = sa1111_chip_driver(sadev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) unsigned int div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) if (sadev->devid != SA1111_DEVID_SAC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) div = (__sa1111_pll_clock(sachip) / 256 + rate / 2) / rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) if (div == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) if (div > 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) div = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) writel_relaxed(div - 1, sachip->base + SA1111_SKAUD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) EXPORT_SYMBOL(sa1111_set_audio_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) * sa1111_get_audio_rate - get the audio sample rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) * @sadev: SA1111 SAC function block device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) int sa1111_get_audio_rate(struct sa1111_dev *sadev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) struct sa1111 *sachip = sa1111_chip_driver(sadev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) unsigned long div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) if (sadev->devid != SA1111_DEVID_SAC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) div = readl_relaxed(sachip->base + SA1111_SKAUD) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) return __sa1111_pll_clock(sachip) / (256 * div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) EXPORT_SYMBOL(sa1111_get_audio_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) * Individual device operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) * sa1111_enable_device - enable an on-chip SA1111 function block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) * @sadev: SA1111 function block device to enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) int sa1111_enable_device(struct sa1111_dev *sadev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) struct sa1111 *sachip = sa1111_chip_driver(sadev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) if (sachip->pdata && sachip->pdata->enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) ret = sachip->pdata->enable(sachip->pdata->data, sadev->devid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) if (ret == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) spin_lock_irqsave(&sachip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) val = readl_relaxed(sachip->base + SA1111_SKPCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) writel_relaxed(val | sadev->skpcr_mask, sachip->base + SA1111_SKPCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) spin_unlock_irqrestore(&sachip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) EXPORT_SYMBOL(sa1111_enable_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) * sa1111_disable_device - disable an on-chip SA1111 function block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) * @sadev: SA1111 function block device to disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) void sa1111_disable_device(struct sa1111_dev *sadev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) struct sa1111 *sachip = sa1111_chip_driver(sadev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) spin_lock_irqsave(&sachip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) val = readl_relaxed(sachip->base + SA1111_SKPCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) writel_relaxed(val & ~sadev->skpcr_mask, sachip->base + SA1111_SKPCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) spin_unlock_irqrestore(&sachip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) if (sachip->pdata && sachip->pdata->disable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) sachip->pdata->disable(sachip->pdata->data, sadev->devid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) EXPORT_SYMBOL(sa1111_disable_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) int sa1111_get_irq(struct sa1111_dev *sadev, unsigned num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) struct sa1111 *sachip = sa1111_chip_driver(sadev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) if (num >= ARRAY_SIZE(sadev->hwirq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) return sa1111_map_irq(sachip, sadev->hwirq[num]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) EXPORT_SYMBOL_GPL(sa1111_get_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) * SA1111 "Register Access Bus."
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) * We model this as a regular bus type, and hang devices directly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) * off this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) static int sa1111_match(struct device *_dev, struct device_driver *_drv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) struct sa1111_dev *dev = to_sa1111_device(_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) struct sa1111_driver *drv = SA1111_DRV(_drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) return !!(dev->devid & drv->devid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) static int sa1111_bus_probe(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) struct sa1111_dev *sadev = to_sa1111_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) struct sa1111_driver *drv = SA1111_DRV(dev->driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) int ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) if (drv->probe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) ret = drv->probe(sadev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) static int sa1111_bus_remove(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) struct sa1111_dev *sadev = to_sa1111_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) struct sa1111_driver *drv = SA1111_DRV(dev->driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) if (drv->remove)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) ret = drv->remove(sadev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) struct bus_type sa1111_bus_type = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) .name = "sa1111-rab",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) .match = sa1111_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) .probe = sa1111_bus_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) .remove = sa1111_bus_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) EXPORT_SYMBOL(sa1111_bus_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) int sa1111_driver_register(struct sa1111_driver *driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) driver->drv.bus = &sa1111_bus_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) return driver_register(&driver->drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) EXPORT_SYMBOL(sa1111_driver_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) void sa1111_driver_unregister(struct sa1111_driver *driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) driver_unregister(&driver->drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) EXPORT_SYMBOL(sa1111_driver_unregister);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) #ifdef CONFIG_DMABOUNCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) * According to the "Intel StrongARM SA-1111 Microprocessor Companion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) * Chip Specification Update" (June 2000), erratum #7, there is a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) * significant bug in the SA1111 SDRAM shared memory controller. If
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) * an access to a region of memory above 1MB relative to the bank base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) * it is important that address bit 10 _NOT_ be asserted. Depending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) * on the configuration of the RAM, bit 10 may correspond to one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) * of several different (processor-relative) address bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) * This routine only identifies whether or not a given DMA address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) * is susceptible to the bug.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) * This should only get called for sa1111_device types due to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) * way we configure our device dma_masks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) static int sa1111_needs_bounce(struct device *dev, dma_addr_t addr, size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) * Section 4.6 of the "Intel StrongARM SA-1111 Development Module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) * User's Guide" mentions that jumpers R51 and R52 control the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) * target of SA-1111 DMA (either SDRAM bank 0 on Assabet, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) * SDRAM bank 1 on Neponset). The default configuration selects
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) * Assabet, so any address in bank 1 is necessarily invalid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) return (machine_is_assabet() || machine_is_pfs168()) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) (addr >= 0xc8000000 || (addr + size) >= 0xc8000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) static int sa1111_notifier_call(struct notifier_block *n, unsigned long action,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) struct sa1111_dev *dev = to_sa1111_device(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) switch (action) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) case BUS_NOTIFY_ADD_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) if (dev->dev.dma_mask && dev->dma_mask < 0xffffffffUL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) int ret = dmabounce_register_dev(&dev->dev, 1024, 4096,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) sa1111_needs_bounce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) dev_err(&dev->dev, "failed to register with dmabounce: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) case BUS_NOTIFY_DEL_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) if (dev->dev.dma_mask && dev->dma_mask < 0xffffffffUL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) dmabounce_unregister_dev(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) static struct notifier_block sa1111_bus_notifier = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) .notifier_call = sa1111_notifier_call,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) static int __init sa1111_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) int ret = bus_register(&sa1111_bus_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) #ifdef CONFIG_DMABOUNCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) bus_register_notifier(&sa1111_bus_type, &sa1111_bus_notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) platform_driver_register(&sa1111_device_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) static void __exit sa1111_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) platform_driver_unregister(&sa1111_device_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) #ifdef CONFIG_DMABOUNCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) bus_unregister_notifier(&sa1111_bus_type, &sa1111_bus_notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) bus_unregister(&sa1111_bus_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) subsys_initcall(sa1111_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) module_exit(sa1111_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) MODULE_DESCRIPTION("Intel Corporation SA1111 core driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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