Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /* 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * linux/arch/arm/boot/compressed/head-sa1100.S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 1999 Nicolas Pitre <nico@fluxnic.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * SA1100 specific tweaks.  This is merged into head.S by the linker.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 		.section        ".start", "ax"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 		.arch	armv4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) __SA1100_start:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 		@ Preserve r8/r7 i.e. kernel entry values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #ifdef CONFIG_SA1100_COLLIE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 		mov	r7, #MACH_TYPE_COLLIE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #ifdef CONFIG_SA1100_SIMPAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 		@ UNTIL we've something like an open bootldr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 		mov	r7, #MACH_TYPE_SIMPAD	@should be 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		mrc	p15, 0, r0, c1, c0, 0	@ read control reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		ands	r0, r0, #0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		beq	99f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		@ Data cache might be active.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		@ Be sure to flush kernel binary out of the cache,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		@ whatever state it is, before it is turned off.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		@ This is done by fetching through currently executed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		@ memory to be sure we hit the same cache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		bic	r2, pc, #0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		add	r3, r2, #0x4000		@ 16 kb is quite enough...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 1:		ldr	r0, [r2], #32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		teq	r2, r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		bne	1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		mcr	p15, 0, r0, c7, c10, 4	@ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		mcr	p15, 0, r0, c7, c7, 0	@ flush I & D caches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		@ disabling MMU and caches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		mrc	p15, 0, r0, c1, c0, 0	@ read control reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		bic	r0, r0, #0x0d		@ clear WB, DC, MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		bic	r0, r0, #0x1000		@ clear Icache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		mcr	p15, 0, r0, c1, c0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 99: