^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ARC HSDK Platform support code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of_fdt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/libfdt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/arcregs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/mach_desc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) int arc_hsdk_axi_dmac_coherent __section(".data") = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define ARC_CCM_UNUSED_ADDR 0x60000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define ARC_PERIPHERAL_BASE 0xf0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CREG_BASE (ARC_PERIPHERAL_BASE + 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SDIO_BASE (ARC_PERIPHERAL_BASE + 0xA000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SDIO_UHS_REG_EXT (SDIO_BASE + 0x108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SDIO_UHS_REG_EXT_DIV_2 (2 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define HSDK_GPIO_INTC (ARC_PERIPHERAL_BASE + 0x3000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static void __init hsdk_enable_gpio_intc_wire(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * Peripherals on CPU Card are wired to cpu intc via intermediate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * DW APB GPIO blocks (mainly for debouncing)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * ---------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * | snps,archs-intc |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * ---------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * ----------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * | snps,archs-idu-intc |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * ----------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * | | | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * | [eth] [USB] [... other peripherals]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * -------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * | snps,dw-apb-intc |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * -------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * | | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * [Bt] [HAPS] [... other peripherals]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * Current implementation of "irq-dw-apb-ictl" driver doesn't work well
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * with stacked INTCs. In particular problem happens if its master INTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * not yet instantiated. See discussion here -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * https://lkml.org/lkml/2015/3/4/755
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * So setup the first gpio block as a passive pass thru and hide it from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * DT hardware topology - connect intc directly to cpu intc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * The GPIO "wire" needs to be init nevertheless (here)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * One side adv is that peripheral interrupt handling avoids one nested
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * intc ISR hop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * According to HSDK User's Manual [1], "Table 2 Interrupt Mapping"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * we have the following GPIO input lines used as sources of interrupt:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * - GPIO[0] - Bluetooth interrupt of RS9113 module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * - GPIO[2] - HAPS interrupt (on HapsTrak 3 connector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * - GPIO[3] - Audio codec (MAX9880A) interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * - GPIO[8-23] - Available on Arduino and PMOD_x headers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * For now there's no use of Arduino and PMOD_x headers in Linux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * use-case so we only enable lines 0, 2 and 3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * [1] https://github.com/foss-for-synopsys-dwc-arc-processors/ARC-Development-Systems-Forum/wiki/docs/ARC_HSDK_User_Guide.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define GPIO_INTEN (HSDK_GPIO_INTC + 0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define GPIO_INTMASK (HSDK_GPIO_INTC + 0x34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define GPIO_INTTYPE_LEVEL (HSDK_GPIO_INTC + 0x38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define GPIO_INT_POLARITY (HSDK_GPIO_INTC + 0x3c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define GPIO_INT_CONNECTED_MASK 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) iowrite32(0xffffffff, (void __iomem *) GPIO_INTMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) iowrite32(~GPIO_INT_CONNECTED_MASK, (void __iomem *) GPIO_INTMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) iowrite32(0x00000000, (void __iomem *) GPIO_INTTYPE_LEVEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) iowrite32(0xffffffff, (void __iomem *) GPIO_INT_POLARITY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) iowrite32(GPIO_INT_CONNECTED_MASK, (void __iomem *) GPIO_INTEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static int __init hsdk_tweak_node_coherency(const char *path, bool coherent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) void *fdt = initial_boot_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) const void *prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) int node, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) bool dt_coh_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) node = fdt_path_offset(fdt, path);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (node < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) goto tweak_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) prop = fdt_getprop(fdt, node, "dma-coherent", &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (!prop && ret != -FDT_ERR_NOTFOUND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) goto tweak_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) dt_coh_set = ret != -FDT_ERR_NOTFOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* need to remove "dma-coherent" property */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (dt_coh_set && !coherent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ret = fdt_delprop(fdt, node, "dma-coherent");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* need to set "dma-coherent" property */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (!dt_coh_set && coherent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) ret = fdt_setprop(fdt, node, "dma-coherent", NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) goto tweak_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) tweak_fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) pr_err("failed to tweak %s to %scoherent\n", path, coherent ? "" : "non");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) enum hsdk_axi_masters {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) M_HS_CORE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) M_HS_RTT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) M_AXI_TUN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) M_HDMI_VIDEO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) M_HDMI_AUDIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) M_USB_HOST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) M_ETHERNET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) M_SDIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) M_GPU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) M_DMAC_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) M_DMAC_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) M_DVFS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define UPDATE_VAL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * This is modified configuration of AXI bridge. Default settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * are specified in "Table 111 CREG Address Decoder register reset values".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * AXI_M_m_SLV{0|1} - Slave Select register for master 'm'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * Possible slaves are:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * - 0 => no slave selected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * - 1 => DDR controller port #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * - 2 => SRAM controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * - 3 => AXI tunnel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * - 4 => EBI controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * - 5 => ROM controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * - 6 => AXI2APB bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * - 7 => DDR controller port #2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * - 8 => DDR controller port #3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * - 9 => HS38x4 IOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * - 10 => HS38x4 DMI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * AXI_M_m_OFFSET{0|1} - Addr Offset register for master 'm'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * Please read ARC HS Development IC Specification, section 17.2 for more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * information about apertures configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * m master AXI_M_m_SLV0 AXI_M_m_SLV1 AXI_M_m_OFFSET0 AXI_M_m_OFFSET1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * 0 HS (CBU) 0x11111111 0x63111111 0xFEDCBA98 0x0E543210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * 1 HS (RTT) 0x77777777 0x77777777 0xFEDCBA98 0x76543210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * 2 AXI Tunnel 0x88888888 0x88888888 0xFEDCBA98 0x76543210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * 3 HDMI-VIDEO 0x77777777 0x77777777 0xFEDCBA98 0x76543210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * 4 HDMI-ADUIO 0x77777777 0x77777777 0xFEDCBA98 0x76543210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * 5 USB-HOST 0x77777777 0x77999999 0xFEDCBA98 0x76DCBA98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * 6 ETHERNET 0x77777777 0x77999999 0xFEDCBA98 0x76DCBA98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * 7 SDIO 0x77777777 0x77999999 0xFEDCBA98 0x76DCBA98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * 8 GPU 0x77777777 0x77777777 0xFEDCBA98 0x76543210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * 9 DMAC (port #1) 0x77777777 0x77777777 0xFEDCBA98 0x76543210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * 10 DMAC (port #2) 0x77777777 0x77777777 0xFEDCBA98 0x76543210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * 11 DVFS 0x00000000 0x60000000 0x00000000 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define CREG_AXI_M_SLV0(m) ((void __iomem *)(CREG_BASE + 0x20 * (m)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define CREG_AXI_M_SLV1(m) ((void __iomem *)(CREG_BASE + 0x20 * (m) + 0x04))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define CREG_AXI_M_OFT0(m) ((void __iomem *)(CREG_BASE + 0x20 * (m) + 0x08))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define CREG_AXI_M_OFT1(m) ((void __iomem *)(CREG_BASE + 0x20 * (m) + 0x0C))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define CREG_AXI_M_UPDT(m) ((void __iomem *)(CREG_BASE + 0x20 * (m) + 0x14))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define CREG_AXI_M_HS_CORE_BOOT ((void __iomem *)(CREG_BASE + 0x010))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define CREG_PAE ((void __iomem *)(CREG_BASE + 0x180))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define CREG_PAE_UPDT ((void __iomem *)(CREG_BASE + 0x194))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static void __init hsdk_init_memory_bridge_axi_dmac(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) bool coherent = !!arc_hsdk_axi_dmac_coherent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) u32 axi_m_slv1, axi_m_oft1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * Don't tweak memory bridge configuration if we failed to tweak DTB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * as we will end up in a inconsistent state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (hsdk_tweak_node_coherency("/soc/dmac@80000", coherent))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (coherent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) axi_m_slv1 = 0x77999999;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) axi_m_oft1 = 0x76DCBA98;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) axi_m_slv1 = 0x77777777;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) axi_m_oft1 = 0x76543210;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) writel(axi_m_slv1, CREG_AXI_M_SLV1(M_DMAC_0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) writel(axi_m_oft1, CREG_AXI_M_OFT1(M_DMAC_0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) writel(axi_m_slv1, CREG_AXI_M_SLV1(M_DMAC_1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) writel(axi_m_oft1, CREG_AXI_M_OFT1(M_DMAC_1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static void __init hsdk_init_memory_bridge(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * M_HS_CORE has one unique register - BOOT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * We need to clean boot mirror (BOOT[1:0]) bits in them to avoid first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * aperture to be masked by 'boot mirror'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) reg = readl(CREG_AXI_M_HS_CORE_BOOT) & (~0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) writel(reg, CREG_AXI_M_HS_CORE_BOOT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) writel(0x11111111, CREG_AXI_M_SLV0(M_HS_CORE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) writel(0x63111111, CREG_AXI_M_SLV1(M_HS_CORE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_CORE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) writel(0x0E543210, CREG_AXI_M_OFT1(M_HS_CORE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_CORE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) writel(0x77777777, CREG_AXI_M_SLV0(M_HS_RTT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) writel(0x77777777, CREG_AXI_M_SLV1(M_HS_RTT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_RTT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) writel(0x76543210, CREG_AXI_M_OFT1(M_HS_RTT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_RTT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) writel(0x88888888, CREG_AXI_M_SLV0(M_AXI_TUN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) writel(0x88888888, CREG_AXI_M_SLV1(M_AXI_TUN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_AXI_TUN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) writel(0x76543210, CREG_AXI_M_OFT1(M_AXI_TUN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_AXI_TUN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) writel(0x77777777, CREG_AXI_M_SLV0(M_HDMI_VIDEO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) writel(0x77777777, CREG_AXI_M_SLV1(M_HDMI_VIDEO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HDMI_VIDEO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) writel(0x76543210, CREG_AXI_M_OFT1(M_HDMI_VIDEO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HDMI_VIDEO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) writel(0x77777777, CREG_AXI_M_SLV0(M_HDMI_AUDIO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) writel(0x77777777, CREG_AXI_M_SLV1(M_HDMI_AUDIO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HDMI_AUDIO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) writel(0x76543210, CREG_AXI_M_OFT1(M_HDMI_AUDIO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HDMI_AUDIO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) writel(0x77777777, CREG_AXI_M_SLV0(M_USB_HOST));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) writel(0x77999999, CREG_AXI_M_SLV1(M_USB_HOST));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_USB_HOST));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) writel(0x76DCBA98, CREG_AXI_M_OFT1(M_USB_HOST));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_USB_HOST));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) writel(0x77777777, CREG_AXI_M_SLV0(M_ETHERNET));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) writel(0x77999999, CREG_AXI_M_SLV1(M_ETHERNET));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_ETHERNET));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) writel(0x76DCBA98, CREG_AXI_M_OFT1(M_ETHERNET));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_ETHERNET));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) writel(0x77777777, CREG_AXI_M_SLV0(M_SDIO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) writel(0x77999999, CREG_AXI_M_SLV1(M_SDIO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_SDIO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) writel(0x76DCBA98, CREG_AXI_M_OFT1(M_SDIO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_SDIO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) writel(0x77777777, CREG_AXI_M_SLV0(M_GPU));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) writel(0x77777777, CREG_AXI_M_SLV1(M_GPU));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_GPU));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) writel(0x76543210, CREG_AXI_M_OFT1(M_GPU));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_GPU));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) writel(0x00000000, CREG_AXI_M_SLV0(M_DVFS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) writel(0x60000000, CREG_AXI_M_SLV1(M_DVFS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) writel(0x00000000, CREG_AXI_M_OFT0(M_DVFS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) writel(0x00000000, CREG_AXI_M_OFT1(M_DVFS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DVFS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) hsdk_init_memory_bridge_axi_dmac();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * PAE remapping for DMA clients does not work due to an RTL bug, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * CREG_PAE register must be programmed to all zeroes, otherwise it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * will cause problems with DMA to/from peripherals even if PAE40 is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * not used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) writel(0x00000000, CREG_PAE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) writel(UPDATE_VAL, CREG_PAE_UPDT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static void __init hsdk_init_early(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) hsdk_init_memory_bridge();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * Switch SDIO external ciu clock divider from default div-by-8 to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * minimum possible div-by-2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) iowrite32(SDIO_UHS_REG_EXT_DIV_2, (void __iomem *) SDIO_UHS_REG_EXT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) hsdk_enable_gpio_intc_wire();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static const char *hsdk_compat[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) "snps,hsdk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) MACHINE_START(SIMULATION, "hsdk")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .dt_compat = hsdk_compat,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .init_early = hsdk_init_early,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) MACHINE_END
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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