^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * AXS101/AXS103 Software Development Platform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/of_fdt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/libfdt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/asm-offsets.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/mach_desc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <soc/arc/mcip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define AXS_MB_CGU 0xE0010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define AXS_MB_CREG 0xE0011000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CREG_MB_IRQ_MUX (AXS_MB_CREG + 0x214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CREG_MB_SW_RESET (AXS_MB_CREG + 0x220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CREG_MB_VER (AXS_MB_CREG + 0x230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CREG_MB_CONFIG (AXS_MB_CREG + 0x234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define AXC001_CREG 0xF0001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define AXC001_GPIO_INTC 0xF0003000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static void __init axs10x_enable_gpio_intc_wire(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * Peripherals on CPU Card and Mother Board are wired to cpu intc via
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * intermediate DW APB GPIO blocks (mainly for debouncing)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * ---------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * | snps,arc700-intc |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * ---------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * | #7 | #15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * ------------------- -------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * | snps,dw-apb-gpio | | snps,dw-apb-gpio |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * ------------------- -------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * | #12 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * | [ Debug UART on cpu card ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * ------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * | snps,dw-apb-intc (MB)|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * ------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * | | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * [eth] [uart] [... other perip on Main Board]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * Current implementation of "irq-dw-apb-ictl" driver doesn't work well
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * with stacked INTCs. In particular problem happens if its master INTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * not yet instantiated. See discussion here -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * https://lkml.org/lkml/2015/3/4/755
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * So setup the first gpio block as a passive pass thru and hide it from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * DT hardware topology - connect MB intc directly to cpu intc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * The GPIO "wire" needs to be init nevertheless (here)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * One side adv is that peripheral interrupt handling avoids one nested
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * intc ISR hop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define GPIO_INTEN (AXC001_GPIO_INTC + 0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define GPIO_INTMASK (AXC001_GPIO_INTC + 0x34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define GPIO_INTTYPE_LEVEL (AXC001_GPIO_INTC + 0x38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define GPIO_INT_POLARITY (AXC001_GPIO_INTC + 0x3c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MB_TO_GPIO_IRQ 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) iowrite32(~(1 << MB_TO_GPIO_IRQ), (void __iomem *) GPIO_INTMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) iowrite32(0, (void __iomem *) GPIO_INTTYPE_LEVEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) iowrite32(~0, (void __iomem *) GPIO_INT_POLARITY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) iowrite32(1 << MB_TO_GPIO_IRQ, (void __iomem *) GPIO_INTEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static void __init axs10x_print_board_ver(unsigned int creg, const char *str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) union ver {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #ifdef CONFIG_CPU_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned int pad:11, y:12, m:4, d:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) unsigned int d:5, m:4, y:12, pad:11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) } board;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) board.val = ioread32((void __iomem *)creg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) pr_info("AXS: %s FPGA Date: %u-%u-%u\n", str, board.d, board.m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) board.y);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static void __init axs10x_early_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int mb_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) char mb[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* Determine motherboard version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (ioread32((void __iomem *) CREG_MB_CONFIG) & (1 << 28))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) mb_rev = 3; /* HT-3 (rev3.0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) mb_rev = 2; /* HT-2 (rev2.0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) axs10x_enable_gpio_intc_wire();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) scnprintf(mb, 32, "MainBoard v%d", mb_rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) axs10x_print_board_ver(CREG_MB_VER, mb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #ifdef CONFIG_AXS101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CREG_CPU_ADDR_770 (AXC001_CREG + 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CREG_CPU_ADDR_TUNN (AXC001_CREG + 0x60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CREG_CPU_ADDR_770_UPD (AXC001_CREG + 0x34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CREG_CPU_ADDR_TUNN_UPD (AXC001_CREG + 0x74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CREG_CPU_ARC770_IRQ_MUX (AXC001_CREG + 0x114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CREG_CPU_GPIO_UART_MUX (AXC001_CREG + 0x120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * Set up System Memory Map for ARC cpu / peripherals controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * Each AXI master has a 4GB memory map specified as 16 apertures of 256MB, each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * of which maps to a corresponding 256MB aperture in Target slave memory map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * e.g. ARC cpu AXI Master's aperture 8 (0x8000_0000) is mapped to aperture 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * (0x0000_0000) of DDR Port 0 (slave #1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * Access from cpu to MB controllers such as GMAC is setup using AXI Tunnel:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * which has master/slaves on both ends.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * e.g. aperture 14 (0xE000_0000) of ARC cpu is mapped to aperture 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * (0xE000_0000) of CPU Card AXI Tunnel slave (slave #3) which is mapped to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * MB AXI Tunnel Master, which also has a mem map setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * In the reverse direction, MB AXI Masters (e.g. GMAC) mem map is setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * to map to MB AXI Tunnel slave which connects to CPU Card AXI Tunnel Master
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct aperture {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) unsigned int slave_sel:4, slave_off:4, pad:24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* CPU Card target slaves */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define AXC001_SLV_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define AXC001_SLV_DDR_PORT0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define AXC001_SLV_SRAM 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define AXC001_SLV_AXI_TUNNEL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define AXC001_SLV_AXI2APB 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define AXC001_SLV_DDR_PORT1 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* MB AXI Target slaves */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define AXS_MB_SLV_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define AXS_MB_SLV_AXI_TUNNEL_CPU 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define AXS_MB_SLV_AXI_TUNNEL_HAPS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define AXS_MB_SLV_SRAM 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define AXS_MB_SLV_CONTROL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* MB AXI masters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define AXS_MB_MST_TUNNEL_CPU 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define AXS_MB_MST_USB_OHCI 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * memmap for ARC core on CPU Card
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static const struct aperture axc001_memmap[16] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {AXC001_SLV_AXI_TUNNEL, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {AXC001_SLV_AXI_TUNNEL, 0x1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {AXC001_SLV_SRAM, 0x0}, /* 0x2000_0000: Local SRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {AXC001_SLV_NONE, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {AXC001_SLV_NONE, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {AXC001_SLV_NONE, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {AXC001_SLV_NONE, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {AXC001_SLV_NONE, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {AXC001_SLV_DDR_PORT0, 0x0}, /* 0x8000_0000: DDR 0..256M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {AXC001_SLV_DDR_PORT0, 0x1}, /* 0x9000_0000: DDR 256..512M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {AXC001_SLV_DDR_PORT0, 0x2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {AXC001_SLV_DDR_PORT0, 0x3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {AXC001_SLV_NONE, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {AXC001_SLV_AXI_TUNNEL, 0xD},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {AXC001_SLV_AXI_TUNNEL, 0xE}, /* MB: CREG, CGU... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {AXC001_SLV_AXI2APB, 0x0}, /* CPU Card local CREG, CGU... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * memmap for CPU Card AXI Tunnel Master (for access by MB controllers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * GMAC (MB) -> MB AXI Tunnel slave -> CPU Card AXI Tunnel Master -> DDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static const struct aperture axc001_axi_tunnel_memmap[16] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {AXC001_SLV_AXI_TUNNEL, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {AXC001_SLV_AXI_TUNNEL, 0x1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {AXC001_SLV_SRAM, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {AXC001_SLV_NONE, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {AXC001_SLV_NONE, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {AXC001_SLV_NONE, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {AXC001_SLV_NONE, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {AXC001_SLV_NONE, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {AXC001_SLV_DDR_PORT1, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {AXC001_SLV_DDR_PORT1, 0x1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {AXC001_SLV_DDR_PORT1, 0x2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {AXC001_SLV_DDR_PORT1, 0x3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {AXC001_SLV_NONE, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {AXC001_SLV_AXI_TUNNEL, 0xD},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {AXC001_SLV_AXI_TUNNEL, 0xE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {AXC001_SLV_AXI2APB, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * memmap for MB AXI Masters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * Same mem map for all perip controllers as well as MB AXI Tunnel Master
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static const struct aperture axs_mb_memmap[16] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {AXS_MB_SLV_SRAM, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {AXS_MB_SLV_SRAM, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {AXS_MB_SLV_NONE, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {AXS_MB_SLV_NONE, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {AXS_MB_SLV_NONE, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {AXS_MB_SLV_NONE, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {AXS_MB_SLV_NONE, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {AXS_MB_SLV_NONE, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {AXS_MB_SLV_AXI_TUNNEL_CPU, 0x8}, /* DDR on CPU Card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {AXS_MB_SLV_AXI_TUNNEL_CPU, 0x9}, /* DDR on CPU Card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {AXS_MB_SLV_AXI_TUNNEL_CPU, 0xA},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {AXS_MB_SLV_AXI_TUNNEL_CPU, 0xB},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {AXS_MB_SLV_NONE, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {AXS_MB_SLV_AXI_TUNNEL_HAPS, 0xD},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {AXS_MB_SLV_CONTROL, 0x0}, /* MB Local CREG, CGU... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {AXS_MB_SLV_AXI_TUNNEL_CPU, 0xF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static noinline void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) axs101_set_memmap(void __iomem *base, const struct aperture map[16])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) unsigned int slave_select, slave_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) slave_select = slave_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) for (i = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) slave_select |= map[i].slave_sel << (i << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) slave_offset |= map[i].slave_off << (i << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) iowrite32(slave_select, base + 0x0); /* SLV0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) iowrite32(slave_offset, base + 0x8); /* OFFSET0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) slave_select = slave_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) for (i = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) slave_select |= map[i+8].slave_sel << (i << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) slave_offset |= map[i+8].slave_off << (i << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) iowrite32(slave_select, base + 0x4); /* SLV1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) iowrite32(slave_offset, base + 0xC); /* OFFSET1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static void __init axs101_early_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* ARC 770D memory view */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) axs101_set_memmap((void __iomem *) CREG_CPU_ADDR_770, axc001_memmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) iowrite32(1, (void __iomem *) CREG_CPU_ADDR_770_UPD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* AXI tunnel memory map (incoming traffic from MB into CPU Card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) axs101_set_memmap((void __iomem *) CREG_CPU_ADDR_TUNN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) axc001_axi_tunnel_memmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) iowrite32(1, (void __iomem *) CREG_CPU_ADDR_TUNN_UPD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* MB peripherals memory map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) for (i = AXS_MB_MST_TUNNEL_CPU; i <= AXS_MB_MST_USB_OHCI; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) axs101_set_memmap((void __iomem *) AXS_MB_CREG + (i << 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) axs_mb_memmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) iowrite32(0x3ff, (void __iomem *) AXS_MB_CREG + 0x100); /* Update */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* GPIO pins 18 and 19 are used as UART rx and tx, respectively. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) iowrite32(0x01, (void __iomem *) CREG_CPU_GPIO_UART_MUX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* Set up the MB interrupt system: mux interrupts to GPIO7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) iowrite32(0x01, (void __iomem *) CREG_MB_IRQ_MUX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* reset ethernet and ULPI interfaces */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) iowrite32(0x18, (void __iomem *) CREG_MB_SW_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* map GPIO 14:10 to ARC 9:5 (IRQ mux change for MB v2 onwards) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) iowrite32(0x52, (void __iomem *) CREG_CPU_ARC770_IRQ_MUX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) axs10x_early_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #endif /* CONFIG_AXS101 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #ifdef CONFIG_AXS103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define AXC003_CREG 0xF0001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define AXC003_MST_AXI_TUNNEL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define AXC003_MST_HS38 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define CREG_CPU_AXI_M0_IRQ_MUX (AXC003_CREG + 0x440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define CREG_CPU_GPIO_UART_MUX (AXC003_CREG + 0x480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define CREG_CPU_TUN_IO_CTRL (AXC003_CREG + 0x494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static void __init axs103_early_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #ifdef CONFIG_ARC_MCIP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * AXS103 configurations for SMP/QUAD configurations share device tree
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * which defaults to 100 MHz. However recent failures of Quad config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * revealed P&R timing violations so clamp it down to safe 50 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * Instead of duplicating defconfig/DT for SMP/QUAD, add a small hack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * of fudging the freq in DT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define AXS103_QUAD_CORE_CPU_FREQ_HZ 50000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) unsigned int num_cores = (read_aux_reg(ARC_REG_MCIP_BCR) >> 16) & 0x3F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (num_cores > 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) u32 freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) int off = fdt_path_offset(initial_boot_params, "/cpu_card/core_clk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) const struct fdt_property *prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) prop = fdt_get_property(initial_boot_params, off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) "assigned-clock-rates", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) freq = be32_to_cpu(*(u32 *)(prop->data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* Patching .dtb in-place with new core clock value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (freq != AXS103_QUAD_CORE_CPU_FREQ_HZ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) freq = cpu_to_be32(AXS103_QUAD_CORE_CPU_FREQ_HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) fdt_setprop_inplace(initial_boot_params, off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) "assigned-clock-rates", &freq, sizeof(freq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /* Memory maps already config in pre-bootloader */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* set GPIO mux to UART */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) iowrite32(0x01, (void __iomem *) CREG_CPU_GPIO_UART_MUX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) iowrite32((0x00100000U | 0x000C0000U | 0x00003322U),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) (void __iomem *) CREG_CPU_TUN_IO_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* Set up the AXS_MB interrupt system.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) iowrite32(12, (void __iomem *) (CREG_CPU_AXI_M0_IRQ_MUX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) + (AXC003_MST_HS38 << 2)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* connect ICTL - Main Board with GPIO line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) iowrite32(0x01, (void __iomem *) CREG_MB_IRQ_MUX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) axs10x_print_board_ver(AXC003_CREG + 4088, "AXC003 CPU Card");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) axs10x_early_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #ifdef CONFIG_AXS101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static const char *axs101_compat[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) "snps,axs101",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) MACHINE_START(AXS101, "axs101")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .dt_compat = axs101_compat,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .init_early = axs101_early_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) MACHINE_END
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #endif /* CONFIG_AXS101 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #ifdef CONFIG_AXS103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static const char *axs103_compat[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) "snps,axs103",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) MACHINE_START(AXS103, "axs103")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .dt_compat = axs103_compat,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .init_early = axs103_early_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) MACHINE_END
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * For the VDK OS-kit, to get the offset to pid and command fields
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) char coware_swa_pid_offset[TASK_PID];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) char coware_swa_comm_offset[TASK_COMM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #endif /* CONFIG_AXS103 */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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