^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * TLB Exception Handling for ARC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Vineetg: April 2011 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * -MMU v1: moved out legacy code into a seperate file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * helps avoid a shift when preparing PD0 from PTE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Vineetg: July 2009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * -For MMU V2, we need not do heuristics at the time of commiting a D-TLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * entry, so that it doesn't knock out it's I-TLB entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * -Some more fine tuning:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * bmsk instead of add, asl.cc instead of branch, delay slot utilise etc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Vineetg: July 2009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * -Practically rewrote the I/D TLB Miss handlers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * Now 40 and 135 instructions a peice as compared to 131 and 449 resp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Hence Leaner by 1.5 K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Used Conditional arithmetic to replace excessive branching
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * Also used short instructions wherever possible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Vineetg: Aug 13th 2008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * -Passing ECR (Exception Cause REG) to do_page_fault( ) for printing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * more information in case of a Fatality
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * Vineetg: March 25th Bug #92690
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * -Added Debug Code to check if sw-ASID == hw-ASID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * Rahul Trivedi, Amit Bhor: Codito Technologies 2004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/pgtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <asm/entry.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <asm/mmu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <asm/arcregs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <asm/cache.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <asm/processor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <asm/tlb-mmu1.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #ifdef CONFIG_ISA_ARCOMPACT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) ;-----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) ; ARC700 Exception Handling doesn't auto-switch stack and it only provides
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) ; ONE scratch AUX reg "ARC_REG_SCRATCH_DATA0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) ; For Non-SMP, the scratch AUX reg is repurposed to cache task PGD, so a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) ; "global" is used to free-up FIRST core reg to be able to code the rest of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) ; exception prologue (IRQ auto-disabled on Exceptions, so it's IRQ-safe).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) ; Since the Fast Path TLB Miss handler is coded with 4 regs, the remaining 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) ; need to be saved as well by extending the "global" to be 4 words. Hence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) ; ".size ex_saved_reg1, 16"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) ; [All of this dance is to avoid stack switching for each TLB Miss, since we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) ; only need to save only a handful of regs, as opposed to complete reg file]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ; For ARC700 SMP, the "global" obviously can't be used for free up the FIRST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) ; core reg as it will not be SMP safe.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) ; Thus scratch AUX reg is used (and no longer used to cache task PGD).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) ; To save the rest of 3 regs - per cpu, the global is made "per-cpu".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) ; Epilogue thus has to locate the "per-cpu" storage for regs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) ; To avoid cache line bouncing the per-cpu global is aligned/sized per
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) ; L1_CACHE_SHIFT, despite fundamentally needing to be 12 bytes only. Hence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) ; ".size ex_saved_reg1, (CONFIG_NR_CPUS << L1_CACHE_SHIFT)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) ; As simple as that....
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) ;--------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) ; scratch memory to save [r0-r3] used to code TLB refill Handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) ARCFP_DATA ex_saved_reg1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .align 1 << L1_CACHE_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .type ex_saved_reg1, @object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .size ex_saved_reg1, (CONFIG_NR_CPUS << L1_CACHE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ex_saved_reg1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .zero (CONFIG_NR_CPUS << L1_CACHE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .size ex_saved_reg1, 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) ex_saved_reg1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .zero 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .macro TLBMISS_FREEUP_REGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) sr r0, [ARC_REG_SCRATCH_DATA0] ; freeup r0 to code with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) GET_CPU_ID r0 ; get to per cpu scratch mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) asl r0, r0, L1_CACHE_SHIFT ; cache line wide per cpu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) add r0, @ex_saved_reg1, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) st r0, [@ex_saved_reg1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) mov_s r0, @ex_saved_reg1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) st_s r1, [r0, 4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) st_s r2, [r0, 8]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) st_s r3, [r0, 12]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) ; VERIFY if the ASID in MMU-PID Reg is same as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ; one in Linux data structures
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) tlb_paranoid_check_asm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .macro TLBMISS_RESTORE_REGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) GET_CPU_ID r0 ; get to per cpu scratch mem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) asl r0, r0, L1_CACHE_SHIFT ; each is cache line wide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) add r0, @ex_saved_reg1, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) ld_s r3, [r0,12]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ld_s r2, [r0, 8]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ld_s r1, [r0, 4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) lr r0, [ARC_REG_SCRATCH_DATA0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) mov_s r0, @ex_saved_reg1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) ld_s r3, [r0,12]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) ld_s r2, [r0, 8]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) ld_s r1, [r0, 4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) ld_s r0, [r0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #else /* ARCv2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .macro TLBMISS_FREEUP_REGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #ifdef CONFIG_ARC_HAS_LL64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) std r0, [sp, -16]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) std r2, [sp, -8]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) PUSH r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) PUSH r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) PUSH r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) PUSH r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .macro TLBMISS_RESTORE_REGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #ifdef CONFIG_ARC_HAS_LL64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ldd r0, [sp, -16]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) ldd r2, [sp, -8]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) POP r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) POP r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) POP r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) POP r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) ;============================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ; Troubleshooting Stuff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) ;============================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ; Linux keeps ASID (Address Space ID) in task->active_mm->context.asid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ; When Creating TLB Entries, instead of doing 3 dependent loads from memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ; we use the MMU PID Reg to get current ASID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ; In bizzare scenrios SW and HW ASID can get out-of-sync which is trouble.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) ; So we try to detect this in TLB Mis shandler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .macro tlb_paranoid_check_asm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #ifdef CONFIG_ARC_DBG_TLB_PARANOIA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) GET_CURR_TASK_ON_CPU r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ld r0, [r3, TASK_ACT_MM]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ld r0, [r0, MM_CTXT+MM_CTXT_ASID]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) breq r0, 0, 55f ; Error if no ASID allocated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) lr r1, [ARC_REG_PID]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) and r1, r1, 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) and r2, r0, 0xFF ; MMU PID bits only for comparison
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) breq r1, r2, 5f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 55:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) ; Error if H/w and S/w ASID don't match, but NOT if in kernel mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) lr r2, [erstatus]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) bbit0 r2, STATUS_U_BIT, 5f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ; We sure are in troubled waters, Flag the error, but to do so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ; need to switch to kernel mode stack to call error routine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) GET_TSK_STACK_BASE r3, sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ; Call printk to shoutout aloud
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) mov r2, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) j print_asid_mismatch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 5: ; ASIDs match so proceed normally
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ;============================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) ;TLB Miss handling Code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) ;============================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) ;-----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) ; This macro does the page-table lookup for the faulting address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) ; OUT: r0 = PTE faulted on, r1 = ptr to PTE, r2 = Faulting V-address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .macro LOAD_FAULT_PTE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) lr r2, [efa]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #ifdef ARC_USE_SCRATCH_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) lr r1, [ARC_REG_SCRATCH_DATA0] ; current pgd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) GET_CURR_TASK_ON_CPU r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ld r1, [r1, TASK_ACT_MM]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) ld r1, [r1, MM_PGD]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) lsr r0, r2, PGDIR_SHIFT ; Bits for indexing into PGD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) ld.as r3, [r1, r0] ; PGD entry corresp to faulting addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) tst r3, r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) bz do_slow_path_pf ; if no Page Table, do page fault
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #ifdef CONFIG_TRANSPARENT_HUGEPAGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) and.f 0, r3, _PAGE_HW_SZ ; Is this Huge PMD (thp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) add2.nz r1, r1, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) bnz.d 2f ; YES: PGD == PMD has THP PTE: stop pgd walk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) mov.nz r0, r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) and r1, r3, PAGE_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ; Get the PTE entry: The idea is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) ; (1) x = addr >> PAGE_SHIFT -> masks page-off bits from @fault-addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ; (2) y = x & (PTRS_PER_PTE - 1) -> to get index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ; (3) z = (pgtbl + y * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #ifdef CONFIG_ARC_HAS_PAE40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define PTE_SIZE_LOG 3 /* 8 == 2 ^ 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define PTE_SIZE_LOG 2 /* 4 == 2 ^ 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) ; multiply in step (3) above avoided by shifting lesser in step (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) lsr r0, r2, ( PAGE_SHIFT - PTE_SIZE_LOG )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) and r0, r0, ( (PTRS_PER_PTE - 1) << PTE_SIZE_LOG )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ld.aw r0, [r1, r0] ; r0: PTE (lower word only for PAE40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ; r1: PTE ptr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) ;-----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) ; Convert Linux PTE entry into TLB entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) ; A one-word PTE entry is programmed as two-word TLB Entry [PD0:PD1] in mmu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) ; (for PAE40, two-words PTE, while three-word TLB Entry [PD0:PD1:PD1HI])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) ; IN: r0 = PTE, r1 = ptr to PTE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .macro CONV_PTE_TO_TLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) and r3, r0, PTE_BITS_RWX ; r w x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) asl r2, r3, 3 ; Kr Kw Kx 0 0 0 (GLOBAL, kernel only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) and.f 0, r0, _PAGE_GLOBAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) or.z r2, r2, r3 ; Kr Kw Kx Ur Uw Ux (!GLOBAL, user page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) and r3, r0, PTE_BITS_NON_RWX_IN_PD1 ; Extract PFN+cache bits from PTE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) or r3, r3, r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) sr r3, [ARC_REG_TLBPD1] ; paddr[31..13] | Kr Kw Kx Ur Uw Ux | C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #ifdef CONFIG_ARC_HAS_PAE40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) ld r3, [r1, 4] ; paddr[39..32]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) sr r3, [ARC_REG_TLBPD1HI]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) and r2, r0, PTE_BITS_IN_PD0 ; Extract other PTE flags: (V)alid, (G)lb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) lr r3,[ARC_REG_TLBPD0] ; MMU prepares PD0 with vaddr and asid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) or r3, r3, r2 ; S | vaddr | {sasid|asid}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) sr r3,[ARC_REG_TLBPD0] ; rewrite PD0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) ;-----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) ; Commit the TLB entry into MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .macro COMMIT_ENTRY_TO_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #if (CONFIG_ARC_MMU_VER < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* Get free TLB slot: Set = computed from vaddr, way = random */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) sr TLBGetIndex, [ARC_REG_TLBCOMMAND]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* Commit the Write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) sr TLBWriteNI, [ARC_REG_TLBCOMMAND]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) sr TLBInsertEntry, [ARC_REG_TLBCOMMAND]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 88:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) ARCFP_CODE ;Fast Path Code, candidate for ICCM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) ;-----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) ; I-TLB Miss Exception Handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) ;-----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) ENTRY(EV_TLBMissI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) TLBMISS_FREEUP_REGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) ;----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) ; Get the PTE corresponding to V-addr accessed, r2 is setup with EFA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) LOAD_FAULT_PTE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) ;----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ; VERIFY_PTE: Check if PTE permissions approp for executing code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) cmp_s r2, VMALLOC_START
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) mov_s r2, (_PAGE_PRESENT | _PAGE_EXECUTE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) or.hs r2, r2, _PAGE_GLOBAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) and r3, r0, r2 ; Mask out NON Flag bits from PTE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) xor.f r3, r3, r2 ; check ( ( pte & flags_test ) == flags_test )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) bnz do_slow_path_pf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) ; Let Linux VM know that the page was accessed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) or r0, r0, _PAGE_ACCESSED ; set Accessed Bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) st_s r0, [r1] ; Write back PTE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) CONV_PTE_TO_TLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) COMMIT_ENTRY_TO_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) TLBMISS_RESTORE_REGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) EV_TLBMissI_fast_ret: ; additional label for VDK OS-kit instrumentation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) rtie
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) END(EV_TLBMissI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) ;-----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) ; D-TLB Miss Exception Handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) ;-----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) ENTRY(EV_TLBMissD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) TLBMISS_FREEUP_REGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) ;----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) ; Get the PTE corresponding to V-addr accessed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) ; If PTE exists, it will setup, r0 = PTE, r1 = Ptr to PTE, r2 = EFA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) LOAD_FAULT_PTE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) ;----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) ; VERIFY_PTE: Chk if PTE permissions approp for data access (R/W/R+W)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) cmp_s r2, VMALLOC_START
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) mov_s r2, _PAGE_PRESENT ; common bit for K/U PTE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) or.hs r2, r2, _PAGE_GLOBAL ; kernel PTE only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) ; Linux PTE [RWX] bits are semantically overloaded:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) ; -If PAGE_GLOBAL set, they refer to kernel-only flags (vmalloc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) ; -Otherwise they are user-mode permissions, and those are exactly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) ; same for kernel mode as well (e.g. copy_(to|from)_user)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) lr r3, [ecr]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) btst_s r3, ECR_C_BIT_DTLB_LD_MISS ; Read Access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) or.nz r2, r2, _PAGE_READ ; chk for Read flag in PTE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) btst_s r3, ECR_C_BIT_DTLB_ST_MISS ; Write Access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) or.nz r2, r2, _PAGE_WRITE ; chk for Write flag in PTE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) ; Above laddering takes care of XCHG access (both R and W)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) ; By now, r2 setup with all the Flags we need to check in PTE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) and r3, r0, r2 ; Mask out NON Flag bits from PTE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) brne.d r3, r2, do_slow_path_pf ; is ((pte & flags_test) == flags_test)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) ;----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) ; UPDATE_PTE: Let Linux VM know that page was accessed/dirty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) or r0, r0, _PAGE_ACCESSED ; Accessed bit always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) or.nz r0, r0, _PAGE_DIRTY ; if Write, set Dirty bit as well
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) st_s r0, [r1] ; Write back PTE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) CONV_PTE_TO_TLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #if (CONFIG_ARC_MMU_VER == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) ; MMU with 2 way set assoc J-TLB, needs some help in pathetic case of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) ; memcpy where 3 parties contend for 2 ways, ensuing a livelock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) ; But only for old MMU or one with Metal Fix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) TLB_WRITE_HEURISTICS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) COMMIT_ENTRY_TO_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) TLBMISS_RESTORE_REGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) EV_TLBMissD_fast_ret: ; additional label for VDK OS-kit instrumentation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) rtie
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ;-------- Common routine to call Linux Page Fault Handler -----------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) do_slow_path_pf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #ifdef CONFIG_ISA_ARCV2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ; Set Z flag if exception in U mode. Hardware micro-ops do this on any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) ; taken interrupt/exception, and thus is already the case at the entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) ; above, but ensuing code would have already clobbered.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) ; EXCEPTION_PROLOGUE called in slow path, relies on correct Z flag set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) lr r2, [erstatus]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) and r2, r2, STATUS_U_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) bxor.f 0, r2, STATUS_U_BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) ; Restore the 4-scratch regs saved by fast path miss handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) TLBMISS_RESTORE_REGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) ; Slow path TLB Miss handled as a regular ARC Exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) ; (stack switching / save the complete reg-file).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) b call_do_page_fault
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) END(EV_TLBMissD)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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