^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * TLB Management (flush/create/diagnostics) for ARC700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * vineetg: Aug 2011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * -Reintroduce duplicate PD fixup - some customer chips still have the issue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * vineetg: May 2011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * -No need to flush_cache_page( ) for each call to update_mmu_cache()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * some of the LMBench tests improved amazingly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * = page-fault thrice as fast (75 usec to 28 usec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * = mmap twice as fast (9.6 msec to 4.6 msec),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * = fork (5.3 msec to 3.7 msec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * vineetg: April 2011 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * helps avoid a shift when preparing PD0 from PTE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * vineetg: April 2011 : Preparing for MMU V3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * -MMU v2/v3 BCRs decoded differently
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * -Remove TLB_SIZE hardcoding as it's variable now: 256 or 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * -tlb_entry_erase( ) can be void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * -local_flush_tlb_range( ):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * = need not "ceil" @end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * = walks MMU only if range spans < 32 entries, as opposed to 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * Vineetg: Sept 10th 2008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * -Changes related to MMU v2 (Rel 4.8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * Vineetg: Aug 29th 2008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * -In TLB Flush operations (Metal Fix MMU) there is a explicit command to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * flush Micro-TLBS. If TLB Index Reg is invalid prior to TLBIVUTLB cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * it fails. Thus need to load it with ANY valid value before invoking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * TLBIVUTLB cmd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * Vineetg: Aug 21th 2008:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * -Reduced the duration of IRQ lockouts in TLB Flush routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * -Multiple copies of TLB erase code separated into a "single" function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * -In TLB Flush routines, interrupt disabling moved UP to retrieve ASID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * in interrupt-safe region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * Vineetg: April 23rd Bug #93131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * Problem: tlb_flush_kernel_range() doesn't do anything if the range to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * flush is more than the size of TLB itself.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * Rahul Trivedi : Codito Technologies 2004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include <linux/bug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include <linux/mm_types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #include <asm/arcregs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #include <asm/setup.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #include <asm/mmu_context.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #include <asm/mmu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* Need for ARC MMU v2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * ARC700 MMU-v1 had a Joint-TLB for Code and Data and is 2 way set-assoc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * For a memcpy operation with 3 players (src/dst/code) such that all 3 pages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * map into same set, there would be contention for the 2 ways causing severe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * Thrashing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * Although J-TLB is 2 way set assoc, ARC700 caches J-TLB into uTLBS which has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * much higher associativity. u-D-TLB is 8 ways, u-I-TLB is 4 ways.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * Given this, the thrashing problem should never happen because once the 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * J-TLB entries are created (even though 3rd will knock out one of the prev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * two), the u-D-TLB and u-I-TLB will have what is required to accomplish memcpy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * Yet we still see the Thrashing because a J-TLB Write cause flush of u-TLBs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * This is a simple design for keeping them in sync. So what do we do?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * The solution which James came up was pretty neat. It utilised the assoc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * of uTLBs by not invalidating always but only when absolutely necessary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * - Existing TLB commands work as before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * - New command (TLBWriteNI) for TLB write without clearing uTLBs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * - New command (TLBIVUTLB) to invalidate uTLBs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * The uTLBs need only be invalidated when pages are being removed from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * OS page table. If a 'victim' TLB entry is being overwritten in the main TLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * as a result of a miss, the removed entry is still allowed to exist in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * uTLBs as it is still valid and present in the OS page table. This allows the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * full associativity of the uTLBs to hide the limited associativity of the main
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * TLB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * During a miss handler, the new "TLBWriteNI" command is used to load
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * entries without clearing the uTLBs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * When the OS page table is updated, TLB entries that may be associated with a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * removed page are removed (flushed) from the TLB using TLBWrite. In this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * circumstance, the uTLBs must also be cleared. This is done by using the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * existing TLBWrite command. An explicit IVUTLB is also required for those
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * corner cases when TLBWrite was not executed at all because the corresp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * J-TLB entry got evicted/replaced.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* A copy of the ASID from the PID reg is kept in asid_cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) DEFINE_PER_CPU(unsigned int, asid_cache) = MM_CTXT_FIRST_CYCLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static int __read_mostly pae_exists;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * Utility Routine to erase a J-TLB entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * Caller needs to setup Index Reg (manually or via getIndex)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static inline void __tlb_entry_erase(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) write_aux_reg(ARC_REG_TLBPD1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (is_pae40_enabled())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) write_aux_reg(ARC_REG_TLBPD1HI, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) write_aux_reg(ARC_REG_TLBPD0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static void utlb_invalidate(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #if (CONFIG_ARC_MMU_VER >= 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #if (CONFIG_ARC_MMU_VER == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* MMU v2 introduced the uTLB Flush command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * There was however an obscure hardware bug, where uTLB flush would
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * fail when a prior probe for J-TLB (both totally unrelated) would
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * return lkup err - because the entry didn't exist in MMU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * The Workaround was to set Index reg with some valid value, prior to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * flush. This was fixed in MMU v3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) unsigned int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* make sure INDEX Reg is valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) idx = read_aux_reg(ARC_REG_TLBINDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* If not write some dummy val */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (unlikely(idx & TLB_LKUP_ERR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) write_aux_reg(ARC_REG_TLBINDEX, 0xa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) write_aux_reg(ARC_REG_TLBCOMMAND, TLBIVUTLB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #if (CONFIG_ARC_MMU_VER < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static inline unsigned int tlb_entry_lkup(unsigned long vaddr_n_asid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) unsigned int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) write_aux_reg(ARC_REG_TLBPD0, vaddr_n_asid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) write_aux_reg(ARC_REG_TLBCOMMAND, TLBProbe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) idx = read_aux_reg(ARC_REG_TLBINDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static void tlb_entry_erase(unsigned int vaddr_n_asid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) unsigned int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* Locate the TLB entry for this vaddr + ASID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) idx = tlb_entry_lkup(vaddr_n_asid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* No error means entry found, zero it out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (likely(!(idx & TLB_LKUP_ERR))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) __tlb_entry_erase();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* Duplicate entry error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) WARN(idx == TLB_DUP_ERR, "Probe returned Dup PD for %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) vaddr_n_asid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static void tlb_entry_insert(unsigned int pd0, pte_t pd1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) unsigned int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * First verify if entry for this vaddr+ASID already exists
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * This also sets up PD0 (vaddr, ASID..) for final commit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) idx = tlb_entry_lkup(pd0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * If Not already present get a free slot from MMU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * Otherwise, Probe would have located the entry and set INDEX Reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * with existing location. This will cause Write CMD to over-write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * existing entry with new PD0 and PD1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (likely(idx & TLB_LKUP_ERR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) write_aux_reg(ARC_REG_TLBCOMMAND, TLBGetIndex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* setup the other half of TLB entry (pfn, rwx..) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) write_aux_reg(ARC_REG_TLBPD1, pd1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * Commit the Entry to MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * It doesn't sound safe to use the TLBWriteNI cmd here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * which doesn't flush uTLBs. I'd rather be safe than sorry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #else /* CONFIG_ARC_MMU_VER >= 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static void tlb_entry_erase(unsigned int vaddr_n_asid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) write_aux_reg(ARC_REG_TLBPD0, vaddr_n_asid | _PAGE_PRESENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) write_aux_reg(ARC_REG_TLBCOMMAND, TLBDeleteEntry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static void tlb_entry_insert(unsigned int pd0, pte_t pd1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) write_aux_reg(ARC_REG_TLBPD0, pd0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) write_aux_reg(ARC_REG_TLBPD1, pd1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (is_pae40_enabled())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) write_aux_reg(ARC_REG_TLBPD1HI, (u64)pd1 >> 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) write_aux_reg(ARC_REG_TLBCOMMAND, TLBInsertEntry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * Un-conditionally (without lookup) erase the entire MMU contents
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) noinline void local_flush_tlb_all(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) unsigned int entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) int num_tlb = mmu->sets * mmu->ways;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* Load PD0 and PD1 with template for a Blank Entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) write_aux_reg(ARC_REG_TLBPD1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (is_pae40_enabled())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) write_aux_reg(ARC_REG_TLBPD1HI, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) write_aux_reg(ARC_REG_TLBPD0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) for (entry = 0; entry < num_tlb; entry++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* write this entry to the TLB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) write_aux_reg(ARC_REG_TLBINDEX, entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) write_aux_reg(ARC_REG_TLBCOMMAND, TLBWriteNI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (IS_ENABLED(CONFIG_TRANSPARENT_HUGEPAGE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) const int stlb_idx = 0x800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* Blank sTLB entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) write_aux_reg(ARC_REG_TLBPD0, _PAGE_HW_SZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) for (entry = stlb_idx; entry < stlb_idx + 16; entry++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) write_aux_reg(ARC_REG_TLBINDEX, entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) write_aux_reg(ARC_REG_TLBCOMMAND, TLBWriteNI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) utlb_invalidate();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * Flush the entire MM for userland. The fastest way is to move to Next ASID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) noinline void local_flush_tlb_mm(struct mm_struct *mm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * Small optimisation courtesy IA64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * flush_mm called during fork,exit,munmap etc, multiple times as well.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * Only for fork( ) do we need to move parent to a new MMU ctxt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * all other cases are NOPs, hence this check.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (atomic_read(&mm->mm_users) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * - Move to a new ASID, but only if the mm is still wired in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * (Android Binder ended up calling this for vma->mm != tsk->mm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * causing h/w - s/w ASID to get out of sync)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * - Also get_new_mmu_context() new implementation allocates a new
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * ASID only if it is not allocated already - so unallocate first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) destroy_context(mm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (current->mm == mm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) get_new_mmu_context(mm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * Flush a Range of TLB entries for userland.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * @start is inclusive, while @end is exclusive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * Difference between this and Kernel Range Flush is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * -Here the fastest way (if range is too large) is to move to next ASID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * without doing any explicit Shootdown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * -In case of kernel Flush, entry has to be shot down explicitly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) unsigned long end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) const unsigned int cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* If range @start to @end is more than 32 TLB entries deep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * its better to move to a new ASID rather than searching for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * individual entries and then shooting them down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * The calc above is rough, doesn't account for unaligned parts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * since this is heuristics based anyways
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (unlikely((end - start) >= PAGE_SIZE * 32)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) local_flush_tlb_mm(vma->vm_mm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * @start moved to page start: this alone suffices for checking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * loop end condition below, w/o need for aligning @end to end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * e.g. 2000 to 4001 will anyhow loop twice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) start &= PAGE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (asid_mm(vma->vm_mm, cpu) != MM_CTXT_NO_ASID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) while (start < end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) tlb_entry_erase(start | hw_pid(vma->vm_mm, cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) start += PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* Flush the kernel TLB entries - vmalloc/modules (Global from MMU perspective)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * @start, @end interpreted as kvaddr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * Interestingly, shared TLB entries can also be flushed using just
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * @start,@end alone (interpreted as user vaddr), although technically SASID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * is also needed. However our smart TLbProbe lookup takes care of that.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /* exactly same as above, except for TLB entry not taking ASID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (unlikely((end - start) >= PAGE_SIZE * 32)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) local_flush_tlb_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) start &= PAGE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) while (start < end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) tlb_entry_erase(start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) start += PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * Delete TLB entry in MMU for a given page (??? address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * NOTE One TLB entry contains translation for single PAGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) const unsigned int cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* Note that it is critical that interrupts are DISABLED between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * checking the ASID and using it flush the TLB entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (asid_mm(vma->vm_mm, cpu) != MM_CTXT_NO_ASID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) tlb_entry_erase((page & PAGE_MASK) | hw_pid(vma->vm_mm, cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) struct tlb_args {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) struct vm_area_struct *ta_vma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) unsigned long ta_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) unsigned long ta_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static inline void ipi_flush_tlb_page(void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct tlb_args *ta = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) local_flush_tlb_page(ta->ta_vma, ta->ta_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static inline void ipi_flush_tlb_range(void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct tlb_args *ta = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) local_flush_tlb_range(ta->ta_vma, ta->ta_start, ta->ta_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #ifdef CONFIG_TRANSPARENT_HUGEPAGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static inline void ipi_flush_pmd_tlb_range(void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) struct tlb_args *ta = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) local_flush_pmd_tlb_range(ta->ta_vma, ta->ta_start, ta->ta_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static inline void ipi_flush_tlb_kernel_range(void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct tlb_args *ta = (struct tlb_args *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) local_flush_tlb_kernel_range(ta->ta_start, ta->ta_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) void flush_tlb_all(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) on_each_cpu((smp_call_func_t)local_flush_tlb_all, NULL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) void flush_tlb_mm(struct mm_struct *mm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) on_each_cpu_mask(mm_cpumask(mm), (smp_call_func_t)local_flush_tlb_mm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) mm, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct tlb_args ta = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .ta_vma = vma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .ta_start = uaddr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) on_each_cpu_mask(mm_cpumask(vma->vm_mm), ipi_flush_tlb_page, &ta, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) unsigned long end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) struct tlb_args ta = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .ta_vma = vma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .ta_start = start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .ta_end = end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) on_each_cpu_mask(mm_cpumask(vma->vm_mm), ipi_flush_tlb_range, &ta, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #ifdef CONFIG_TRANSPARENT_HUGEPAGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) unsigned long end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) struct tlb_args ta = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .ta_vma = vma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .ta_start = start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .ta_end = end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) on_each_cpu_mask(mm_cpumask(vma->vm_mm), ipi_flush_pmd_tlb_range, &ta, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) void flush_tlb_kernel_range(unsigned long start, unsigned long end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) struct tlb_args ta = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .ta_start = start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .ta_end = end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) on_each_cpu(ipi_flush_tlb_kernel_range, &ta, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * Routine to create a TLB entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) void create_tlb(struct vm_area_struct *vma, unsigned long vaddr, pte_t *ptep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) unsigned int asid_or_sasid, rwx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) unsigned long pd0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) pte_t pd1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * create_tlb() assumes that current->mm == vma->mm, since
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * -it ASID for TLB entry is fetched from MMU ASID reg (valid for curr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * -completes the lazy write to SASID reg (again valid for curr tsk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * Removing the assumption involves
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * -Using vma->mm->context{ASID,SASID}, as opposed to MMU reg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * -Fix the TLB paranoid debug code to not trigger false negatives.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * -More importantly it makes this handler inconsistent with fast-path
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) * TLB Refill handler which always deals with "current"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) * Lets see the use cases when current->mm != vma->mm and we land here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) * 1. execve->copy_strings()->__get_user_pages->handle_mm_fault
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * Here VM wants to pre-install a TLB entry for user stack while
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * current->mm still points to pre-execve mm (hence the condition).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * However the stack vaddr is soon relocated (randomization) and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) * move_page_tables() tries to undo that TLB entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) * Thus not creating TLB entry is not any worse.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) * 2. ptrace(POKETEXT) causes a CoW - debugger(current) inserting a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) * breakpoint in debugged task. Not creating a TLB now is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) * performance critical.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) * Both the cases above are not good enough for code churn.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (current->active_mm != vma->vm_mm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) tlb_paranoid_check(asid_mm(vma->vm_mm, smp_processor_id()), vaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) vaddr &= PAGE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* update this PTE credentials */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) pte_val(*ptep) |= (_PAGE_PRESENT | _PAGE_ACCESSED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /* Create HW TLB(PD0,PD1) from PTE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /* ASID for this task */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) asid_or_sasid = read_aux_reg(ARC_REG_PID) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) pd0 = vaddr | asid_or_sasid | (pte_val(*ptep) & PTE_BITS_IN_PD0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) * ARC MMU provides fully orthogonal access bits for K/U mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) * however Linux only saves 1 set to save PTE real-estate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * Here we convert 3 PTE bits into 6 MMU bits:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * -Kernel only entries have Kr Kw Kx 0 0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * -User entries have mirrored K and U bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) rwx = pte_val(*ptep) & PTE_BITS_RWX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (pte_val(*ptep) & _PAGE_GLOBAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) rwx <<= 3; /* r w x => Kr Kw Kx 0 0 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) rwx |= (rwx << 3); /* r w x => Kr Kw Kx Ur Uw Ux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) pd1 = rwx | (pte_val(*ptep) & PTE_BITS_NON_RWX_IN_PD1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) tlb_entry_insert(pd0, pd1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * Called at the end of pagefault, for a userspace mapped page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) * -pre-install the corresponding TLB entry into MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) * -Finalize the delayed D-cache flush of kernel mapping of page due to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) * flush_dcache_page(), copy_user_page()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * Note that flush (when done) involves both WBACK - so physical page is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) * in sync as well as INV - so any non-congruent aliases don't remain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) void update_mmu_cache(struct vm_area_struct *vma, unsigned long vaddr_unaligned,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) pte_t *ptep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) unsigned long vaddr = vaddr_unaligned & PAGE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) phys_addr_t paddr = pte_val(*ptep) & PAGE_MASK_PHYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) struct page *page = pfn_to_page(pte_pfn(*ptep));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) create_tlb(vma, vaddr, ptep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (page == ZERO_PAGE(0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) * Exec page : Independent of aliasing/page-color considerations,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) * since icache doesn't snoop dcache on ARC, any dirty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) * K-mapping of a code page needs to be wback+inv so that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) * icache fetch by userspace sees code correctly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) * !EXEC page: If K-mapping is NOT congruent to U-mapping, flush it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * so userspace sees the right data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) * (Avoids the flush for Non-exec + congruent mapping case)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) if ((vma->vm_flags & VM_EXEC) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) addr_not_cache_congruent(paddr, vaddr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) int dirty = !test_and_set_bit(PG_dc_clean, &page->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (dirty) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) /* wback + inv dcache lines (K-mapping) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) __flush_dcache_page(paddr, paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) /* invalidate any existing icache lines (U-mapping) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) if (vma->vm_flags & VM_EXEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) __inv_icache_page(paddr, vaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #ifdef CONFIG_TRANSPARENT_HUGEPAGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * MMUv4 in HS38x cores supports Super Pages which are basis for Linux THP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) * support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) * Normal and Super pages can co-exist (ofcourse not overlap) in TLB with a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) * new bit "SZ" in TLB page descriptor to distinguish between them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) * Super Page size is configurable in hardware (4K to 16M), but fixed once
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * RTL builds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) * The exact THP size a Linux configuration will support is a function of:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * - MMU page size (typical 8K, RTL fixed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * - software page walker address split between PGD:PTE:PFN (typical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) * 11:8:13, but can be changed with 1 line)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) * So for above default, THP size supported is 8K * (2^8) = 2M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) * Default Page Walker is 2 levels, PGD:PTE:PFN, which in THP regime
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) * reduces to 1 level (as PTE is folded into PGD and canonically referred
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) * to as PMD).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) * Thus THP PMD accessors are implemented in terms of PTE (just like sparc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) pmd_t *pmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) pte_t pte = __pte(pmd_val(*pmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) update_mmu_cache(vma, addr, &pte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) pgtable_t pgtable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) struct list_head *lh = (struct list_head *) pgtable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) assert_spin_locked(&mm->page_table_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) /* FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) if (!pmd_huge_pte(mm, pmdp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) INIT_LIST_HEAD(lh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) list_add(lh, (struct list_head *) pmd_huge_pte(mm, pmdp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) pmd_huge_pte(mm, pmdp) = pgtable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) struct list_head *lh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) pgtable_t pgtable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) assert_spin_locked(&mm->page_table_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) pgtable = pmd_huge_pte(mm, pmdp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) lh = (struct list_head *) pgtable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) if (list_empty(lh))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) pmd_huge_pte(mm, pmdp) = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) pmd_huge_pte(mm, pmdp) = (pgtable_t) lh->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) list_del(lh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) pte_val(pgtable[0]) = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) pte_val(pgtable[1]) = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) return pgtable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) void local_flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) unsigned long end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) unsigned int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (likely(asid_mm(vma->vm_mm, cpu) != MM_CTXT_NO_ASID)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) unsigned int asid = hw_pid(vma->vm_mm, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) /* No need to loop here: this will always be for 1 Huge Page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) tlb_entry_erase(start | _PAGE_HW_SZ | asid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) /* Read the Cache Build Configuration Registers, Decode them and save into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) * the cpuinfo structure for later use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) * No Validation is done here, simply read/convert the BCRs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) void read_decode_mmu_bcr(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) struct bcr_mmu_1_2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #ifdef CONFIG_CPU_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) unsigned int ver:8, ways:4, sets:4, u_itlb:8, u_dtlb:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) unsigned int u_dtlb:8, u_itlb:8, sets:4, ways:4, ver:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) } *mmu2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) struct bcr_mmu_3 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #ifdef CONFIG_CPU_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) unsigned int ver:8, ways:4, sets:4, res:3, sasid:1, pg_sz:4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) u_itlb:4, u_dtlb:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) unsigned int u_dtlb:4, u_itlb:4, pg_sz:4, sasid:1, res:3, sets:4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) ways:4, ver:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) } *mmu3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) struct bcr_mmu_4 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) #ifdef CONFIG_CPU_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) unsigned int ver:8, sasid:1, sz1:4, sz0:4, res:2, pae:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) n_ways:2, n_entry:2, n_super:2, u_itlb:3, u_dtlb:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) /* DTLB ITLB JES JE JA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) unsigned int u_dtlb:3, u_itlb:3, n_super:2, n_entry:2, n_ways:2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) pae:1, res:2, sz0:4, sz1:4, sasid:1, ver:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) } *mmu4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) tmp = read_aux_reg(ARC_REG_MMU_BCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) mmu->ver = (tmp >> 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (is_isa_arcompact()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) if (mmu->ver <= 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) mmu2 = (struct bcr_mmu_1_2 *)&tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) mmu->pg_sz_k = TO_KB(0x2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) mmu->sets = 1 << mmu2->sets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) mmu->ways = 1 << mmu2->ways;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) mmu->u_dtlb = mmu2->u_dtlb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) mmu->u_itlb = mmu2->u_itlb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) mmu3 = (struct bcr_mmu_3 *)&tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) mmu->pg_sz_k = 1 << (mmu3->pg_sz - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) mmu->sets = 1 << mmu3->sets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) mmu->ways = 1 << mmu3->ways;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) mmu->u_dtlb = mmu3->u_dtlb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) mmu->u_itlb = mmu3->u_itlb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) mmu->sasid = mmu3->sasid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) mmu4 = (struct bcr_mmu_4 *)&tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) mmu->pg_sz_k = 1 << (mmu4->sz0 - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) mmu->s_pg_sz_m = 1 << (mmu4->sz1 - 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) mmu->sets = 64 << mmu4->n_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) mmu->ways = mmu4->n_ways * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) mmu->u_dtlb = mmu4->u_dtlb * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) mmu->u_itlb = mmu4->u_itlb * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) mmu->sasid = mmu4->sasid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) pae_exists = mmu->pae = mmu4->pae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) int n = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) struct cpuinfo_arc_mmu *p_mmu = &cpuinfo_arc700[cpu_id].mmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) char super_pg[64] = "";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (p_mmu->s_pg_sz_m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) scnprintf(super_pg, 64, "%dM Super Page %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) p_mmu->s_pg_sz_m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) IS_USED_CFG(CONFIG_TRANSPARENT_HUGEPAGE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) n += scnprintf(buf + n, len - n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) "MMU [v%x]\t: %dk PAGE, %sJTLB %d (%dx%d), uDTLB %d, uITLB %d%s%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) p_mmu->ver, p_mmu->pg_sz_k, super_pg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) p_mmu->sets * p_mmu->ways, p_mmu->sets, p_mmu->ways,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) p_mmu->u_dtlb, p_mmu->u_itlb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) IS_AVAIL2(p_mmu->pae, ", PAE40 ", CONFIG_ARC_HAS_PAE40));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) return buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) int pae40_exist_but_not_enab(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) return pae_exists && !is_pae40_enabled();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) void arc_mmu_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) char str[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) int compat = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) pr_info("%s", arc_mmu_mumbojumbo(0, str, sizeof(str)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) * Can't be done in processor.h due to header include dependencies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) BUILD_BUG_ON(!IS_ALIGNED((CONFIG_ARC_KVADDR_SIZE << 20), PMD_SIZE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) * stack top size sanity check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) * Can't be done in processor.h due to header include dependencies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) BUILD_BUG_ON(!IS_ALIGNED(STACK_TOP, PMD_SIZE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) * Ensure that MMU features assumed by kernel exist in hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) * For older ARC700 cpus, it has to be exact match, since the MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) * revisions were not backwards compatible (MMUv3 TLB layout changed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) * so even if kernel for v2 didn't use any new cmds of v3, it would
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) * still not work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) * For HS cpus, MMUv4 was baseline and v5 is backwards compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) * (will run older software).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) if (is_isa_arcompact() && mmu->ver == CONFIG_ARC_MMU_VER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) compat = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) else if (is_isa_arcv2() && mmu->ver >= CONFIG_ARC_MMU_VER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) compat = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (!compat) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) panic("MMU ver %d doesn't match kernel built for %d...\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) mmu->ver, CONFIG_ARC_MMU_VER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (mmu->pg_sz_k != TO_KB(PAGE_SIZE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) panic("MMU pg size != PAGE_SIZE (%luk)\n", TO_KB(PAGE_SIZE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) if (IS_ENABLED(CONFIG_TRANSPARENT_HUGEPAGE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) mmu->s_pg_sz_m != TO_MB(HPAGE_PMD_SIZE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) panic("MMU Super pg size != Linux HPAGE_PMD_SIZE (%luM)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) (unsigned long)TO_MB(HPAGE_PMD_SIZE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) if (IS_ENABLED(CONFIG_ARC_HAS_PAE40) && !mmu->pae)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) panic("Hardware doesn't support PAE40\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) /* Enable the MMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) write_aux_reg(ARC_REG_PID, MMU_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) /* In smp we use this reg for interrupt 1 scratch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) #ifdef ARC_USE_SCRATCH_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) /* swapper_pg_dir is the pgd for the kernel, used by vmalloc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) write_aux_reg(ARC_REG_SCRATCH_DATA0, swapper_pg_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) if (pae40_exist_but_not_enab())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) write_aux_reg(ARC_REG_TLBPD1HI, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) * TLB Programmer's Model uses Linear Indexes: 0 to {255, 511} for 128 x {2,4}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) * The mapping is Column-first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) * --------------------- -----------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) * |way0|way1|way2|way3| |way0|way1|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) * --------------------- -----------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) * [set0] | 0 | 1 | 2 | 3 | | 0 | 1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) * [set1] | 4 | 5 | 6 | 7 | | 2 | 3 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) * ~ ~ ~ ~
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) * [set127] | 508| 509| 510| 511| | 254| 255|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) * --------------------- -----------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) * For normal operations we don't(must not) care how above works since
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) * MMU cmd getIndex(vaddr) abstracts that out.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) * However for walking WAYS of a SET, we need to know this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) #define SET_WAY_TO_IDX(mmu, set, way) ((set) * mmu->ways + (way))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) /* Handling of Duplicate PD (TLB entry) in MMU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) * -Could be due to buggy customer tapeouts or obscure kernel bugs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) * -MMU complaints not at the time of duplicate PD installation, but at the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) * time of lookup matching multiple ways.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) * -Ideally these should never happen - but if they do - workaround by deleting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) * the duplicate one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) * -Knob to be verbose abt it.(TODO: hook them up to debugfs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) volatile int dup_pd_silent; /* Be silent abt it or complain (default) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) void do_tlb_overlap_fault(unsigned long cause, unsigned long address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) int set, n_ways = mmu->ways;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) n_ways = min(n_ways, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) BUG_ON(mmu->ways > 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) /* loop thru all sets of TLB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) for (set = 0; set < mmu->sets; set++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) int is_valid, way;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) unsigned int pd0[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) /* read out all the ways of current set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) for (way = 0, is_valid = 0; way < n_ways; way++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) write_aux_reg(ARC_REG_TLBINDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) SET_WAY_TO_IDX(mmu, set, way));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) write_aux_reg(ARC_REG_TLBCOMMAND, TLBRead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) pd0[way] = read_aux_reg(ARC_REG_TLBPD0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) is_valid |= pd0[way] & _PAGE_PRESENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) pd0[way] &= PAGE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) /* If all the WAYS in SET are empty, skip to next SET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) if (!is_valid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) /* Scan the set for duplicate ways: needs a nested loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) for (way = 0; way < n_ways - 1; way++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) int n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) if (!pd0[way])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) for (n = way + 1; n < n_ways; n++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) if (pd0[way] != pd0[n])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) if (!dup_pd_silent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) pr_info("Dup TLB PD0 %08x @ set %d ways %d,%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) pd0[way], set, way, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) * clear entry @way and not @n.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) * This is critical to our optimised loop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) pd0[way] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) write_aux_reg(ARC_REG_TLBINDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) SET_WAY_TO_IDX(mmu, set, way));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) __tlb_entry_erase();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) /***********************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) * Diagnostic Routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) * -Called from Low Level TLB Handlers if things don;t look good
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) **********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) #ifdef CONFIG_ARC_DBG_TLB_PARANOIA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) * Low Level ASM TLB handler calls this if it finds that HW and SW ASIDS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) * don't match
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) void print_asid_mismatch(int mm_asid, int mmu_asid, int is_fast_path)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) pr_emerg("ASID Mismatch in %s Path Handler: sw-pid=0x%x hw-pid=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) is_fast_path ? "Fast" : "Slow", mm_asid, mmu_asid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) __asm__ __volatile__("flag 1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) void tlb_paranoid_check(unsigned int mm_asid, unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) unsigned int mmu_asid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) mmu_asid = read_aux_reg(ARC_REG_PID) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) * At the time of a TLB miss/installation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) * - HW version needs to match SW version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) * - SW needs to have a valid ASID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) if (addr < 0x70000000 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) ((mm_asid == MM_CTXT_NO_ASID) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) (mmu_asid != (mm_asid & MM_CTXT_ASID_MASK))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) print_asid_mismatch(mm_asid, mmu_asid, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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