^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/fs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/root_dev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/console.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_fdt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/cache.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <uapi/linux/mount.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/sections.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/arcregs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/asserts.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/tlb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/setup.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/unwind.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/mach_desc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <asm/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <asm/dsp-impl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define FIX_PTR(x) __asm__ __volatile__(";" : "+r"(x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) unsigned int intr_to_DE_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* Part of U-boot ABI: see head.S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) int __initdata uboot_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) int __initdata uboot_magic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) char __initdata *uboot_arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) const struct machine_desc *machine_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct task_struct *_current_task[NR_CPUS]; /* For stack switching */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct cpuinfo_arc cpuinfo_arc700[NR_CPUS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static const struct id_to_str arc_legacy_rel[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* ID.ARCVER, Release */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #ifdef CONFIG_ISA_ARCOMPACT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) { 0x34, "R4.10"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) { 0x35, "R4.11"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) { 0x51, "R2.0" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) { 0x52, "R2.1" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) { 0x53, "R3.0" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) { 0x00, NULL }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static const struct id_to_str arc_hs_ver54_rel[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* UARCH.MAJOR, Release */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) { 0, "R3.10a"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) { 1, "R3.50a"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) { 2, "R3.60a"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) { 3, "R4.00a"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) { 0xFF, NULL }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static void read_decode_ccm_bcr(struct cpuinfo_arc *cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (is_isa_arcompact()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct bcr_iccm_arcompact iccm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct bcr_dccm_arcompact dccm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) READ_BCR(ARC_REG_ICCM_BUILD, iccm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (iccm.ver) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) cpu->iccm.sz = 4096 << iccm.sz; /* 8K to 512K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) cpu->iccm.base_addr = iccm.base << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) READ_BCR(ARC_REG_DCCM_BUILD, dccm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (dccm.ver) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) unsigned long base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) cpu->dccm.sz = 2048 << dccm.sz; /* 2K to 256K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) base = read_aux_reg(ARC_REG_DCCM_BASE_BUILD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) cpu->dccm.base_addr = base & ~0xF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct bcr_iccm_arcv2 iccm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct bcr_dccm_arcv2 dccm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) unsigned long region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) READ_BCR(ARC_REG_ICCM_BUILD, iccm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (iccm.ver) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) cpu->iccm.sz = 256 << iccm.sz00; /* 512B to 16M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (iccm.sz00 == 0xF && iccm.sz01 > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) cpu->iccm.sz <<= iccm.sz01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) region = read_aux_reg(ARC_REG_AUX_ICCM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) cpu->iccm.base_addr = region & 0xF0000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) READ_BCR(ARC_REG_DCCM_BUILD, dccm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (dccm.ver) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) cpu->dccm.sz = 256 << dccm.sz0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (dccm.sz0 == 0xF && dccm.sz1 > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) cpu->dccm.sz <<= dccm.sz1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) region = read_aux_reg(ARC_REG_AUX_DCCM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) cpu->dccm.base_addr = region & 0xF0000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static void decode_arc_core(struct cpuinfo_arc *cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct bcr_uarch_build_arcv2 uarch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) const struct id_to_str *tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (cpu->core.family < 0x54) { /* includes arc700 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) for (tbl = &arc_legacy_rel[0]; tbl->id != 0; tbl++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (cpu->core.family == tbl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) cpu->release = tbl->str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (is_isa_arcompact())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) cpu->name = "ARC700";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) else if (tbl->str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) cpu->name = "HS38";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) cpu->name = cpu->release = "Unknown";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * Initial HS cores bumped AUX IDENTITY.ARCVER for each release until
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * ARCVER 0x54 which introduced AUX MICRO_ARCH_BUILD and subsequent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * releases only update it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) READ_BCR(ARC_REG_MICRO_ARCH_BCR, uarch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (uarch.prod == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) cpu->name = "HS48";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) cpu->extn.dual = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) cpu->name = "HS38";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) for (tbl = &arc_hs_ver54_rel[0]; tbl->id != 0xFF; tbl++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (uarch.maj == tbl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) cpu->release = tbl->str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static void read_arc_build_cfg_regs(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct bcr_timer timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct bcr_generic bcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct bcr_isa_arcv2 isa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct bcr_actionpoint ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) FIX_PTR(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) READ_BCR(AUX_IDENTITY, cpu->core);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) decode_arc_core(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) READ_BCR(ARC_REG_TIMERS_BCR, timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) cpu->extn.timer0 = timer.t0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) cpu->extn.timer1 = timer.t1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) cpu->extn.rtc = timer.rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) cpu->vec_base = read_aux_reg(AUX_INTR_VEC_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) READ_BCR(ARC_REG_MUL_BCR, cpu->extn_mpy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* Read CCM BCRs for boot reporting even if not enabled in Kconfig */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) read_decode_ccm_bcr(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) read_decode_mmu_bcr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) read_decode_cache_bcr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (is_isa_arcompact()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct bcr_fp_arcompact sp, dp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct bcr_bpu_arcompact bpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) READ_BCR(ARC_REG_FP_BCR, sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) READ_BCR(ARC_REG_DPFP_BCR, dp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) cpu->extn.fpu_sp = sp.ver ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) cpu->extn.fpu_dp = dp.ver ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) READ_BCR(ARC_REG_BPU_BCR, bpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) cpu->bpu.ver = bpu.ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) cpu->bpu.full = bpu.fam ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (bpu.ent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) cpu->bpu.num_cache = 256 << (bpu.ent - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) cpu->bpu.num_pred = 256 << (bpu.ent - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct bcr_fp_arcv2 spdp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct bcr_bpu_arcv2 bpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) READ_BCR(ARC_REG_FP_V2_BCR, spdp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) cpu->extn.fpu_sp = spdp.sp ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) cpu->extn.fpu_dp = spdp.dp ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) READ_BCR(ARC_REG_BPU_BCR, bpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) cpu->bpu.ver = bpu.ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) cpu->bpu.full = bpu.ft;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) cpu->bpu.num_cache = 256 << bpu.bce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) cpu->bpu.num_pred = 2048 << bpu.pte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) cpu->bpu.ret_stk = 4 << bpu.rse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* if dual issue hardware, is it enabled ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (cpu->extn.dual) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) unsigned int exec_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) READ_BCR(AUX_EXEC_CTRL, exec_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) cpu->extn.dual_enb = !(exec_ctrl & 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) READ_BCR(ARC_REG_AP_BCR, ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (ap.ver) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) cpu->extn.ap_num = 2 << ap.num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) cpu->extn.ap_full = !ap.min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) READ_BCR(ARC_REG_SMART_BCR, bcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) cpu->extn.smart = bcr.ver ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) READ_BCR(ARC_REG_RTT_BCR, bcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) cpu->extn.rtt = bcr.ver ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) READ_BCR(ARC_REG_ISA_CFG_BCR, isa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* some hacks for lack of feature BCR info in old ARC700 cores */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (is_isa_arcompact()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (!isa.ver) /* ISA BCR absent, use Kconfig info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) cpu->isa.atomic = IS_ENABLED(CONFIG_ARC_HAS_LLSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* ARC700_BUILD only has 2 bits of isa info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct bcr_generic bcr = *(struct bcr_generic *)&isa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) cpu->isa.atomic = bcr.info & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) cpu->isa.be = IS_ENABLED(CONFIG_CPU_BIG_ENDIAN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* there's no direct way to distinguish 750 vs. 770 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (unlikely(cpu->core.family < 0x34 || cpu->mmu.ver < 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) cpu->name = "ARC750";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) cpu->isa = isa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct bcr_identity *core = &cpu->core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) char mpy_opt[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) int n = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) FIX_PTR(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) n += scnprintf(buf + n, len - n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) "\nIDENTITY\t: ARCVER [%#02x] ARCNUM [%#02x] CHIPID [%#4x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) core->family, core->cpu_id, core->chip_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) n += scnprintf(buf + n, len - n, "processor [%d]\t: %s %s (%s ISA) %s%s%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) cpu_id, cpu->name, cpu->release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) is_isa_arcompact() ? "ARCompact" : "ARCv2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) IS_AVAIL1(cpu->isa.be, "[Big-Endian]"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) IS_AVAIL3(cpu->extn.dual, cpu->extn.dual_enb, " Dual-Issue "));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) n += scnprintf(buf + n, len - n, "Timers\t\t: %s%s%s%s%s%s\nISA Extn\t: ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) IS_AVAIL1(cpu->extn.timer0, "Timer0 "),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) IS_AVAIL1(cpu->extn.timer1, "Timer1 "),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) IS_AVAIL2(cpu->extn.rtc, "RTC [UP 64-bit] ", CONFIG_ARC_TIMERS_64BIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) IS_AVAIL2(cpu->extn.gfrc, "GFRC [SMP 64-bit] ", CONFIG_ARC_TIMERS_64BIT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (cpu->extn_mpy.ver) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (is_isa_arcompact()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) scnprintf(mpy_opt, 16, "mpy");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) int opt = 2; /* stock MPY/MPYH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (cpu->extn_mpy.dsp) /* OPT 7-9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) opt = cpu->extn_mpy.dsp + 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) scnprintf(mpy_opt, 16, "mpy[opt %d] ", opt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) n += scnprintf(buf + n, len - n, "%s%s%s%s%s%s%s%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) IS_AVAIL2(cpu->isa.atomic, "atomic ", CONFIG_ARC_HAS_LLSC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) IS_AVAIL2(cpu->isa.ldd, "ll64 ", CONFIG_ARC_HAS_LL64),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) IS_AVAIL2(cpu->isa.unalign, "unalign ", CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) IS_AVAIL1(cpu->extn_mpy.ver, mpy_opt),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) IS_AVAIL1(cpu->isa.div_rem, "div_rem "));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (cpu->bpu.ver) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) n += scnprintf(buf + n, len - n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) "BPU\t\t: %s%s match, cache:%d, Predict Table:%d Return stk: %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) IS_AVAIL1(cpu->bpu.full, "full"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) IS_AVAIL1(!cpu->bpu.full, "partial"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) cpu->bpu.num_cache, cpu->bpu.num_pred, cpu->bpu.ret_stk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (is_isa_arcv2()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct bcr_lpb lpb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) READ_BCR(ARC_REG_LPB_BUILD, lpb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (lpb.ver) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) unsigned int ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) ctl = read_aux_reg(ARC_REG_LPB_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) n += scnprintf(buf + n, len - n, " Loop Buffer:%d %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) lpb.entries,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) IS_DISABLED_RUN(!ctl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) n += scnprintf(buf + n, len - n, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static char *arc_extn_mumbojumbo(int cpu_id, char *buf, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) int n = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) FIX_PTR(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) n += scnprintf(buf + n, len - n, "Vector Table\t: %#x\n", cpu->vec_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (cpu->extn.fpu_sp || cpu->extn.fpu_dp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) n += scnprintf(buf + n, len - n, "FPU\t\t: %s%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) IS_AVAIL1(cpu->extn.fpu_sp, "SP "),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) IS_AVAIL1(cpu->extn.fpu_dp, "DP "));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (cpu->extn.ap_num | cpu->extn.smart | cpu->extn.rtt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) n += scnprintf(buf + n, len - n, "DEBUG\t\t: %s%s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) IS_AVAIL1(cpu->extn.smart, "smaRT "),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) IS_AVAIL1(cpu->extn.rtt, "RTT "));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (cpu->extn.ap_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) n += scnprintf(buf + n, len - n, "ActionPoint %d/%s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) cpu->extn.ap_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) cpu->extn.ap_full ? "full":"min");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) n += scnprintf(buf + n, len - n, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (cpu->dccm.sz || cpu->iccm.sz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) n += scnprintf(buf + n, len - n, "Extn [CCM]\t: DCCM @ %x, %d KB / ICCM: @ %x, %d KB\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) cpu->dccm.base_addr, TO_KB(cpu->dccm.sz),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) cpu->iccm.base_addr, TO_KB(cpu->iccm.sz));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (is_isa_arcv2()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* Error Protection: ECC/Parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct bcr_erp erp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) READ_BCR(ARC_REG_ERP_BUILD, erp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (erp.ver) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) struct ctl_erp ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) READ_BCR(ARC_REG_ERP_CTRL, ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* inverted bits: 0 means enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) n += scnprintf(buf + n, len - n, "Extn [ECC]\t: %s%s%s%s%s%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) IS_AVAIL3(erp.ic, !ctl.dpi, "IC "),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) IS_AVAIL3(erp.dc, !ctl.dpd, "DC "),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) IS_AVAIL3(erp.mmu, !ctl.mpd, "MMU "));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) void chk_opt_strict(char *opt_name, bool hw_exists, bool opt_ena)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (hw_exists && !opt_ena)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) pr_warn(" ! Enable %s for working apps\n", opt_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) else if (!hw_exists && opt_ena)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) panic("Disable %s, hardware NOT present\n", opt_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) void chk_opt_weak(char *opt_name, bool hw_exists, bool opt_ena)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (!hw_exists && opt_ena)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) panic("Disable %s, hardware NOT present\n", opt_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static void arc_chk_core_config(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) int present = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (!cpu->extn.timer0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) panic("Timer0 is not present!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (!cpu->extn.timer1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) panic("Timer1 is not present!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #ifdef CONFIG_ARC_HAS_DCCM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * DCCM can be arbit placed in hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * Make sure it's placement/sz matches what Linux is built with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if ((unsigned int)__arc_dccm_base != cpu->dccm.base_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) panic("Linux built with incorrect DCCM Base address\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (CONFIG_ARC_DCCM_SZ * SZ_1K != cpu->dccm.sz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) panic("Linux built with incorrect DCCM Size\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #ifdef CONFIG_ARC_HAS_ICCM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (CONFIG_ARC_ICCM_SZ * SZ_1K != cpu->iccm.sz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) panic("Linux built with incorrect ICCM Size\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * FP hardware/software config sanity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * -If hardware present, kernel needs to save/restore FPU state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * -If not, it will crash trying to save/restore the non-existant regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (is_isa_arcompact()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /* only DPDP checked since SP has no arch visible regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) present = cpu->extn.fpu_dp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) CHK_OPT_STRICT(CONFIG_ARC_FPU_SAVE_RESTORE, present);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* Accumulator Low:High pair (r58:59) present if DSP MPY or FPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) present = cpu->extn_mpy.dsp | cpu->extn.fpu_sp | cpu->extn.fpu_dp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) CHK_OPT_STRICT(CONFIG_ARC_HAS_ACCL_REGS, present);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) dsp_config_check();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * Initialize and setup the processor core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * This is called by all the CPUs thus should not do special case stuff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * such as only for boot CPU etc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) void setup_processor(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) char str[512];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) int cpu_id = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) read_arc_build_cfg_regs();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) arc_init_IRQ();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) pr_info("%s", arc_cpu_mumbojumbo(cpu_id, str, sizeof(str)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) arc_mmu_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) arc_cache_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) pr_info("%s", arc_extn_mumbojumbo(cpu_id, str, sizeof(str)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) pr_info("%s", arc_platform_smp_cpuinfo());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) arc_chk_core_config();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static inline bool uboot_arg_invalid(unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) * Check that it is a untranslated address (although MMU is not enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * yet, it being a high address ensures this is not by fluke)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (addr < PAGE_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /* Check that address doesn't clobber resident kernel image */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return addr >= (unsigned long)_stext && addr <= (unsigned long)_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define IGNORE_ARGS "Ignore U-boot args: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* uboot_tag values for U-boot - kernel ABI revision 0; see head.S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define UBOOT_TAG_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define UBOOT_TAG_CMDLINE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define UBOOT_TAG_DTB 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /* We always pass 0 as magic from U-boot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define UBOOT_MAGIC_VALUE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) void __init handle_uboot_args(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) bool use_embedded_dtb = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) bool append_cmdline = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /* check that we know this tag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (uboot_tag != UBOOT_TAG_NONE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) uboot_tag != UBOOT_TAG_CMDLINE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) uboot_tag != UBOOT_TAG_DTB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) pr_warn(IGNORE_ARGS "invalid uboot tag: '%08x'\n", uboot_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) goto ignore_uboot_args;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (uboot_magic != UBOOT_MAGIC_VALUE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) pr_warn(IGNORE_ARGS "non zero uboot magic\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) goto ignore_uboot_args;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (uboot_tag != UBOOT_TAG_NONE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) uboot_arg_invalid((unsigned long)uboot_arg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) pr_warn(IGNORE_ARGS "invalid uboot arg: '%px'\n", uboot_arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) goto ignore_uboot_args;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /* see if U-boot passed an external Device Tree blob */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (uboot_tag == UBOOT_TAG_DTB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) machine_desc = setup_machine_fdt((void *)uboot_arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /* external Device Tree blob is invalid - use embedded one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) use_embedded_dtb = !machine_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (uboot_tag == UBOOT_TAG_CMDLINE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) append_cmdline = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) ignore_uboot_args:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (use_embedded_dtb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) machine_desc = setup_machine_fdt(__dtb_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (!machine_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) panic("Embedded DT invalid\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) * NOTE: @boot_command_line is populated by setup_machine_fdt() so this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) * append processing can only happen after.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (append_cmdline) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /* Ensure a whitespace between the 2 cmdlines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) strlcat(boot_command_line, " ", COMMAND_LINE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) strlcat(boot_command_line, uboot_arg, COMMAND_LINE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) void __init setup_arch(char **cmdline_p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) handle_uboot_args();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /* Save unparsed command line copy for /proc/cmdline */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) *cmdline_p = boot_command_line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /* To force early parsing of things like mem=xxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) parse_early_param();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /* Platform/board specific: e.g. early console registration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (machine_desc->init_early)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) machine_desc->init_early();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) smp_init_cpus();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) setup_processor();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) setup_arch_memory();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /* copy flat DT out of .init and then unflatten it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) unflatten_and_copy_device_tree();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) /* Can be issue if someone passes cmd line arg "ro"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) * But that is unlikely so keeping it as it is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) root_mountflags &= ~MS_RDONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) arc_unwind_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) * Called from start_kernel() - boot CPU only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) void __init time_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) of_clk_init(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) timer_probe();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static int __init customize_machine(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (machine_desc->init_machine)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) machine_desc->init_machine();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) arch_initcall(customize_machine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static int __init init_late_machine(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (machine_desc->init_late)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) machine_desc->init_late();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) late_initcall(init_late_machine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * Get CPU information for use by the procfs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define cpu_to_ptr(c) ((void *)(0xFFFF0000 | (unsigned int)(c)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define ptr_to_cpu(p) (~0xFFFF0000UL & (unsigned int)(p))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static int show_cpuinfo(struct seq_file *m, void *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) char *str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) int cpu_id = ptr_to_cpu(v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) struct device *cpu_dev = get_cpu_device(cpu_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) struct clk *cpu_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) unsigned long freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (!cpu_online(cpu_id)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) seq_printf(m, "processor [%d]\t: Offline\n", cpu_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) str = (char *)__get_free_page(GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if (!str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) seq_printf(m, arc_cpu_mumbojumbo(cpu_id, str, PAGE_SIZE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) cpu_clk = clk_get(cpu_dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (IS_ERR(cpu_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) seq_printf(m, "CPU speed \t: Cannot get clock for processor [%d]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) cpu_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) freq = clk_get_rate(cpu_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) seq_printf(m, "CPU speed\t: %lu.%02lu Mhz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) freq / 1000000, (freq / 10000) % 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) seq_printf(m, "Bogo MIPS\t: %lu.%02lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) loops_per_jiffy / (500000 / HZ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) (loops_per_jiffy / (5000 / HZ)) % 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) seq_printf(m, arc_mmu_mumbojumbo(cpu_id, str, PAGE_SIZE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) seq_printf(m, arc_cache_mumbojumbo(cpu_id, str, PAGE_SIZE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) seq_printf(m, arc_extn_mumbojumbo(cpu_id, str, PAGE_SIZE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) seq_printf(m, arc_platform_smp_cpuinfo());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) free_page((unsigned long)str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) seq_printf(m, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static void *c_start(struct seq_file *m, loff_t *pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) * Callback returns cpu-id to iterator for show routine, NULL to stop.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) * However since NULL is also a valid cpu-id (0), we use a round-about
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * way to pass it w/o having to kmalloc/free a 2 byte string.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * Encode cpu-id as 0xFFcccc, which is decoded by show routine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) return *pos < nr_cpu_ids ? cpu_to_ptr(*pos) : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) static void *c_next(struct seq_file *m, void *v, loff_t *pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) ++*pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) return c_start(m, pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) static void c_stop(struct seq_file *m, void *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) const struct seq_operations cpuinfo_op = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .start = c_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .next = c_next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .stop = c_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .show = show_cpuinfo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) static DEFINE_PER_CPU(struct cpu, cpu_topology);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) static int __init topology_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) for_each_present_cpu(cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) register_cpu(&per_cpu(cpu_topology, cpu), cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) subsys_initcall(topology_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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