Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 2011-12 Synopsys, Inc. (www.synopsys.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <asm/mach_desc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <asm/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  * Late Interrupt system init called from start_kernel for Boot CPU only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  * Since slab must already be initialized, platforms can start doing any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  * needed request_irq( )s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) void __init init_IRQ(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	 * process the entire interrupt tree in one go
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	 * Any external intc will be setup provided DT chains them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	 * properly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	irqchip_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	/* a SMP H/w block could do IPI IRQ request here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	if (plat_smp_ops.init_per_cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		plat_smp_ops.init_per_cpu(smp_processor_id());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	if (machine_desc->init_per_cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		machine_desc->init_per_cpu(smp_processor_id());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)  * "C" Entry point for any ARC ISR, called from low level vector handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)  * @irq is the vector number read from ICAUSE reg of on-chip intc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) void arch_do_IRQ(unsigned int hwirq, struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	handle_domain_irq(NULL, hwirq, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }