Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * ARCv2 ISA based core Low Level Intr/Traps/Exceptions(non-TLB) Handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/linkage.h>   /* ARC_{EXTRY,EXIT} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <asm/entry.h>       /* SAVE_ALL_{INT1,INT2,TRAP...} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <asm/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <asm/arcregs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <asm/irqflags.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) ; A maximum number of supported interrupts in the core interrupt controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) ; This number is not equal to the maximum interrupt number (256) because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) ; first 16 lines are reserved for exceptions and are not configurable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define NR_CPU_IRQS	240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	.cpu HS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define VECTOR	.word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) ;############################ Vector Table #################################
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	.section .vector,"a",@progbits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	.align 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) # Initial 16 slots are Exception Vectors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) VECTOR	res_service		; Reset Vector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) VECTOR	mem_service		; Mem exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) VECTOR	instr_service		; Instrn Error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) VECTOR	EV_MachineCheck		; Fatal Machine check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) VECTOR	EV_TLBMissI		; Intruction TLB miss
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) VECTOR	EV_TLBMissD		; Data TLB miss
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) VECTOR	EV_TLBProtV		; Protection Violation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) VECTOR	EV_PrivilegeV		; Privilege Violation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) VECTOR	EV_SWI			; Software Breakpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) VECTOR	EV_Trap			; Trap exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) VECTOR	EV_Extension		; Extn Instruction Exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) VECTOR	EV_DivZero		; Divide by Zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) VECTOR	EV_DCError		; Data Cache Error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) VECTOR	EV_Misaligned		; Misaligned Data Access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) VECTOR	reserved		; Reserved slots
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) VECTOR	reserved		; Reserved slots
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) # Begin Interrupt Vectors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) VECTOR	handle_interrupt	; (16) Timer0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) VECTOR	handle_interrupt	; unused (Timer1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) VECTOR	handle_interrupt	; unused (WDT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) VECTOR	handle_interrupt	; (19) Inter core Interrupt (IPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) VECTOR	handle_interrupt	; (20) perf Interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) VECTOR	handle_interrupt	; (21) Software Triggered Intr (Self IPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) VECTOR	handle_interrupt	; unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) VECTOR	handle_interrupt	; (23) unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) # End of fixed IRQs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) .rept NR_CPU_IRQS - 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	VECTOR	handle_interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) .endr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	.section .text, "ax",@progbits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) reserved:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	flag 1		; Unexpected event, halt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) ;##################### Interrupt Handling ##############################
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) ENTRY(handle_interrupt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	INTERRUPT_PROLOGUE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	# irq control APIs local_irq_save/restore/disable/enable fiddle with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	# global interrupt enable bits in STATUS32 (.IE for 1 prio, .E[] for 2 prio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	# However a taken interrupt doesn't clear these bits. Thus irqs_disabled()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	# query in hard ISR path would return false (since .IE is set) which would
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	# trips genirq interrupt handling asserts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	# So do a "soft" disable of interrutps here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	# Note this disable is only for consistent book-keeping as further interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	# will be disabled anyways even w/o this. Hardware tracks active interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	# seperately in AUX_IRQ_ACT.active and will not take new interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	# unless this one returns (or higher prio becomes pending in 2-prio scheme)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	IRQ_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	; icause is banked: one per priority level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	; so a higher prio interrupt taken here won't clobber prev prio icause
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	lr  r0, [ICAUSE]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	mov   blink, ret_from_exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	b.d  arch_do_IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	mov r1, sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) END(handle_interrupt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) ;################### Non TLB Exception Handling #############################
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) ENTRY(EV_SWI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	; TODO: implement this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	EXCEPTION_PROLOGUE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	b   ret_from_exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) END(EV_SWI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ENTRY(EV_DivZero)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	; TODO: implement this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	EXCEPTION_PROLOGUE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	b   ret_from_exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) END(EV_DivZero)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ENTRY(EV_DCError)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	; TODO: implement this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	EXCEPTION_PROLOGUE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	b   ret_from_exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) END(EV_DCError)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) ; ---------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) ; Memory Error Exception Handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) ;   - Unlike ARCompact, handles Bus errors for both User/Kernel mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) ;     Instruction fetch or Data access, under a single Exception Vector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) ; ---------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) ENTRY(mem_service)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	EXCEPTION_PROLOGUE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	lr  r0, [efa]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	mov r1, sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	FAKE_RET_FROM_EXCPN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	bl  do_memory_error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	b   ret_from_exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) END(mem_service)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) ENTRY(EV_Misaligned)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	EXCEPTION_PROLOGUE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	lr  r0, [efa]	; Faulting Data address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	mov r1, sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	FAKE_RET_FROM_EXCPN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	SAVE_CALLEE_SAVED_USER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	mov r2, sp              ; callee_regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	bl  do_misaligned_access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	; TBD: optimize - do this only if a callee reg was involved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	; either a dst of emulated LD/ST or src with address-writeback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	RESTORE_CALLEE_SAVED_USER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	b   ret_from_exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) END(EV_Misaligned)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ; ---------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) ; Protection Violation Exception Handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ; ---------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ENTRY(EV_TLBProtV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	EXCEPTION_PROLOGUE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	lr  r0, [efa]	; Faulting Data address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	mov r1, sp	; pt_regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	FAKE_RET_FROM_EXCPN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	mov blink, ret_from_exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	b   do_page_fault
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) END(EV_TLBProtV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ; From Linux standpoint Slow Path I/D TLB Miss is same a ProtV as they
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) ; need to call do_page_fault().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ; ECR in pt_regs provides whether access was R/W/X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .global        call_do_page_fault
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .set call_do_page_fault, EV_TLBProtV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ;############# Common Handlers for ARCompact and ARCv2 ##############
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #include "entry.S"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ;############# Return from Intr/Excp/Trap (ARCv2 ISA Specifics) ##############
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ; Restore the saved sys context (common exit-path for EXCPN/IRQ/Trap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ; IRQ shd definitely not happen between now and rtie
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ; All 2 entry points to here already disable interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .Lrestore_regs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) restore_regs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	# Interrpts are actually disabled from this point on, but will get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	# reenabled after we return from interrupt/exception.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	# But irq tracer needs to be told now...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	TRACE_ASM_IRQ_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	ld	r0, [sp, PT_status32]	; U/K mode at time of entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	lr	r10, [AUX_IRQ_ACT]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	bmsk	r11, r10, 15		; extract AUX_IRQ_ACT.active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	breq	r11, 0, .Lexcept_ret	; No intr active, ret from Exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) ;####### Return from Intr #######
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .Lisr_ret:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) debug_marker_l1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	; bbit1.nt r0, STATUS_DE_BIT, .Lintr_ret_to_delay_slot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	btst	r0, STATUS_DE_BIT		; Z flag set if bit clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	bnz	.Lintr_ret_to_delay_slot	; branch if STATUS_DE_BIT set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	; Handle special case #1: (Entry via Exception, Return via IRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	; Exception in U mode, preempted in kernel, Intr taken (K mode), orig
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	; task now returning to U mode (riding the Intr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	; AUX_IRQ_ACTIVE won't have U bit set (since intr in K mode), hence SP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	; won't be switched to correct U mode value (from AUX_SP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	; So force AUX_IRQ_ACT.U for such a case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	btst	r0, STATUS_U_BIT		; Z flag set if K (Z clear for U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	bset.nz	r11, r11, AUX_IRQ_ACT_BIT_U	; NZ means U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	sr	r11, [AUX_IRQ_ACT]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	INTERRUPT_EPILOGUE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	rtie
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ;####### Return from Exception / pure kernel mode #######
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .Lexcept_ret:	; Expects r0 has PT_status32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) debug_marker_syscall:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	EXCEPTION_EPILOGUE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	rtie
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ;####### Return from Intr to insn in delay slot #######
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) ; Handle special case #2: (Entry via Exception in Delay Slot, Return via IRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ; Intr returning to a Delay Slot (DS) insn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ; (since IRQ NOT allowed in DS in ARCv2, this can only happen if orig
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) ; entry was via Exception in DS which got preempted in kernel).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) ; IRQ RTIE won't reliably restore DE bit and/or BTA, needs workaround
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ; Solution is to drop out of interrupt context into pure kernel mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) ; and return from pure kernel mode which does right things for delay slot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .Lintr_ret_to_delay_slot:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) debug_marker_ds:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	ld	r2, [@intr_to_DE_cnt]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	add	r2, r2, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	st	r2, [@intr_to_DE_cnt]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	; drop out of interrupt context (clear AUX_IRQ_ACT.active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	bmskn	r11, r10, 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	sr	r11, [AUX_IRQ_ACT]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	b	.Lexcept_ret
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) END(ret_from_exception)