^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef _ASM_ARC_MMU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define _ASM_ARC_MMU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/threads.h> /* NR_CPUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #if defined(CONFIG_ARC_MMU_V1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CONFIG_ARC_MMU_VER 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #elif defined(CONFIG_ARC_MMU_V2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CONFIG_ARC_MMU_VER 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #elif defined(CONFIG_ARC_MMU_V3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CONFIG_ARC_MMU_VER 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #elif defined(CONFIG_ARC_MMU_V4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CONFIG_ARC_MMU_VER 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* MMU Management regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ARC_REG_MMU_BCR 0x06f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #if (CONFIG_ARC_MMU_VER < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ARC_REG_TLBPD0 0x405
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ARC_REG_TLBPD1 0x406
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ARC_REG_TLBPD1HI 0 /* Dummy: allows code sharing with ARC700 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ARC_REG_TLBINDEX 0x407
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ARC_REG_TLBCOMMAND 0x408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ARC_REG_PID 0x409
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ARC_REG_SCRATCH_DATA0 0x418
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ARC_REG_TLBPD0 0x460
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ARC_REG_TLBPD1 0x461
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ARC_REG_TLBPD1HI 0x463
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ARC_REG_TLBINDEX 0x464
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ARC_REG_TLBCOMMAND 0x465
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ARC_REG_PID 0x468
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ARC_REG_SCRATCH_DATA0 0x46c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #if defined(CONFIG_ISA_ARCV2) || !defined(CONFIG_SMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define ARC_USE_SCRATCH_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* Bits in MMU PID register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define __TLB_ENABLE (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define __PROG_ENABLE (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MMU_ENABLE (__TLB_ENABLE | __PROG_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* Error code if probe fails */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define TLB_LKUP_ERR 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #if (CONFIG_ARC_MMU_VER < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define TLB_DUP_ERR (TLB_LKUP_ERR | 0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define TLB_DUP_ERR (TLB_LKUP_ERR | 0x40000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* TLB Commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define TLBWrite 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define TLBRead 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define TLBGetIndex 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define TLBProbe 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #if (CONFIG_ARC_MMU_VER >= 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define TLBWriteNI 0x5 /* write JTLB without inv uTLBs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define TLBIVUTLB 0x6 /* explicitly inv uTLBs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define TLBWriteNI TLBWrite /* Not present in hardware, fallback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #if (CONFIG_ARC_MMU_VER >= 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define TLBInsertEntry 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define TLBDeleteEntry 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) unsigned long asid[NR_CPUS]; /* 8 bit MMU PID + Generation cycle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) } mm_context_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #ifdef CONFIG_ARC_DBG_TLB_PARANOIA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) void tlb_paranoid_check(unsigned int mm_asid, unsigned long address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define tlb_paranoid_check(a, b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) void arc_mmu_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) extern char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) void read_decode_mmu_bcr(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static inline int is_pae40_enabled(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return IS_ENABLED(CONFIG_ARC_HAS_PAE40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) extern int pae40_exist_but_not_enab(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #endif /* !__ASSEMBLY__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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