Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Vineetg: March 2009 (Supporting 2 levels of Interrupts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *  Stack switching code can no longer reliably rely on the fact that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *  if we are NOT in user mode, stack is switched to kernel mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *  e.g. L2 IRQ interrupted a L1 ISR which had not yet completed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *  it's prologue including stack switching from user mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * Vineetg: Aug 28th 2008: Bug #94984
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *  -Zero Overhead Loop Context shd be cleared when entering IRQ/EXcp/Trap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  *   Normally CPU does this automatically, however when doing FAKE rtie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  *   we also need to explicitly do this. The problem in macros
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  *   FAKE_RET_FROM_EXCPN and FAKE_RET_FROM_EXCPN_LOCK_IRQ was that this bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  *   was being "CLEARED" rather then "SET". Actually "SET" clears ZOL context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * Vineetg: May 5th 2008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  *  -Modified CALLEE_REG save/restore macros to handle the fact that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  *      r25 contains the kernel current task ptr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  *  - Defined Stack Switching Macro to be reused in all intr/excp hdlrs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  *  - Shaved off 11 instructions from RESTORE_ALL_INT1 by using the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  *      address Write back load ld.ab instead of seperate ld/add instn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  * Amit Bhor, Sameer Dhavale: Codito Technologies 2004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #ifndef __ASM_ARC_ENTRY_COMPACT_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define __ASM_ARC_ENTRY_COMPACT_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #include <asm/asm-offsets.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #include <asm/irqflags-compact.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #include <asm/thread_info.h>	/* For THREAD_SIZE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) /*--------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  * Switch to Kernel Mode stack if SP points to User Mode stack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  * Entry   : r9 contains pre-IRQ/exception/trap status32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  * Exit    : SP set to K mode stack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  *           SP at the time of entry (K/U) saved @ pt_regs->sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  * Clobbers: r9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  *-------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) .macro SWITCH_TO_KERNEL_STK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	/* User Mode when this happened ? Yes: Proceed to switch stack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	bbit1   r9, STATUS_U_BIT, 88f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	/* OK we were already in kernel mode when this event happened, thus can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	 * assume SP is kernel mode SP. _NO_ need to do any stack switching
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	/* However....
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	 * If Level 2 Interrupts enabled, we may end up with a corner case:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	 * 1. User Task executing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	 * 2. L1 IRQ taken, ISR starts (CPU auto-switched to KERNEL mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	 * 3. But before it could switch SP from USER to KERNEL stack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	 *      a L2 IRQ "Interrupts" L1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	 * Thay way although L2 IRQ happened in Kernel mode, stack is still
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	 * not switched.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	 * To handle this, we may need to switch stack even if in kernel mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	 * provided SP has values in range of USER mode stack ( < 0x7000_0000 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	brlo sp, VMALLOC_START, 88f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	/* TODO: vineetg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	 * We need to be a bit more cautious here. What if a kernel bug in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	 * L1 ISR, caused SP to go whaco (some small value which looks like
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	 * USER stk) and then we take L2 ISR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	 * Above brlo alone would treat it as a valid L1-L2 scenario
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	 * instead of shouting around
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	 * The only feasible way is to make sure this L2 happened in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	 * L1 prelogue ONLY i.e. ilink2 is less than a pre-set marker in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	 * L1 ISR before it switches stack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81)     /*------Intr/Ecxp happened in kernel mode, SP already setup ------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	/* save it nevertheless @ pt_regs->sp for uniformity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	b.d	66f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	st	sp, [sp, PT_sp - SZ_PT_REGS]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 88: /*------Intr/Ecxp happened in user mode, "switch" stack ------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	GET_CURR_TASK_ON_CPU   r9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	/* With current tsk in r9, get it's kernel mode stack base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	GET_TSK_STACK_BASE  r9, r9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	/* save U mode SP @ pt_regs->sp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	st	sp, [r9, PT_sp - SZ_PT_REGS]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	/* final SP switch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	mov	sp, r9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 66:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /*------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)  * "FAKE" a rtie to return from CPU Exception context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)  * This is to re-enable Exceptions within exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)  * Look at EV_ProtV to see how this is actually used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)  *-------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .macro FAKE_RET_FROM_EXCPN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	lr	r9, [status32]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	bclr	r9, r9, STATUS_AE_BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	or	r9, r9, (STATUS_E1_MASK|STATUS_E2_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	sr	r9, [erstatus]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	mov	r9, 55f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	sr	r9, [eret]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	rtie
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 55:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /*--------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)  * For early Exception/ISR Prologue, a core reg is temporarily needed to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)  * code the rest of prolog (stack switching). This is done by stashing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)  * it to memory (non-SMP case) or SCRATCH0 Aux Reg (SMP).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)  * Before saving the full regfile - this reg is restored back, only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)  * to be saved again on kernel mode stack, as part of pt_regs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)  *-------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .macro PROLOG_FREEUP_REG	reg, mem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #ifndef ARC_USE_SCRATCH_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	sr  \reg, [ARC_REG_SCRATCH_DATA0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	st  \reg, [\mem]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .macro PROLOG_RESTORE_REG	reg, mem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #ifndef ARC_USE_SCRATCH_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	lr  \reg, [ARC_REG_SCRATCH_DATA0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	ld  \reg, [\mem]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /*--------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)  * Exception Entry prologue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)  * -Switches stack to K mode (if not already)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)  * -Saves the register file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)  * After this it is safe to call the "C" handlers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)  *-------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .macro EXCEPTION_PROLOGUE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	/* Need at least 1 reg to code the early exception prologue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	PROLOG_FREEUP_REG r9, @ex_saved_reg1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	/* U/K mode at time of exception (stack not switched if already K) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	lr  r9, [erstatus]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	/* ARC700 doesn't provide auto-stack switching */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	SWITCH_TO_KERNEL_STK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #ifdef CONFIG_ARC_CURR_IN_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	/* Treat r25 as scratch reg (save on stack) and load with "current" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	PUSH    r25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	GET_CURR_TASK_ON_CPU   r25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	sub     sp, sp, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	st.a	r0, [sp, -8]    /* orig_r0 needed for syscall (skip ECR slot) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	sub	sp, sp, 4	/* skip pt_regs->sp, already saved above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	/* Restore r9 used to code the early prologue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	PROLOG_RESTORE_REG  r9, @ex_saved_reg1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	/* now we are ready to save the regfile */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	SAVE_R0_TO_R12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	PUSH	gp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	PUSH	fp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	PUSH	blink
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	PUSHAX	eret
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	PUSHAX	erstatus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	PUSH	lp_count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	PUSHAX	lp_end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	PUSHAX	lp_start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	PUSHAX	erbta
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	lr	r10, [ecr]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	st      r10, [sp, PT_event]    /* EV_Trap expects r10 to have ECR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /*--------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)  * Restore all registers used by system call or Exceptions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)  * SP should always be pointing to the next free stack element
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)  * when entering this macro.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)  * NOTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)  * It is recommended that lp_count/ilink1/ilink2 not be used as a dest reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)  * for memory load operations. If used in that way interrupts are deffered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)  * by hardware and that is not good.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)  *-------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .macro EXCEPTION_EPILOGUE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	POPAX	erbta
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	POPAX	lp_start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	POPAX	lp_end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	POP	r9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	mov	lp_count, r9	;LD to lp_count is not allowed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	POPAX	erstatus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	POPAX	eret
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	POP	blink
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	POP	fp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	POP	gp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	RESTORE_R12_TO_R0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #ifdef CONFIG_ARC_CURR_IN_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	ld	r25, [sp, 12]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	ld  sp, [sp] /* restore original sp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	/* orig_r0, ECR, user_r25 skipped automatically */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* Dummy ECR values for Interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define event_IRQ1		0x0031abcd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define event_IRQ2		0x0032abcd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .macro INTERRUPT_PROLOGUE  LVL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	/* free up r9 as scratchpad */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	PROLOG_FREEUP_REG r9, @int\LVL\()_saved_reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	/* Which mode (user/kernel) was the system in when intr occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	lr  r9, [status32_l\LVL\()]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	SWITCH_TO_KERNEL_STK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #ifdef CONFIG_ARC_CURR_IN_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	/* Treat r25 as scratch reg (save on stack) and load with "current" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	PUSH    r25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	GET_CURR_TASK_ON_CPU   r25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	sub     sp, sp, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	PUSH	0x003\LVL\()abcd    /* Dummy ECR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	sub	sp, sp, 8	    /* skip orig_r0 (not needed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 				       skip pt_regs->sp, already saved above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	/* Restore r9 used to code the early prologue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	PROLOG_RESTORE_REG  r9, @int\LVL\()_saved_reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	SAVE_R0_TO_R12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	PUSH	gp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	PUSH	fp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	PUSH	blink
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	PUSH	ilink\LVL\()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	PUSHAX	status32_l\LVL\()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	PUSH	lp_count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	PUSHAX	lp_end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	PUSHAX	lp_start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	PUSHAX	bta_l\LVL\()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /*--------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)  * Restore all registers used by interrupt handlers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)  * NOTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)  * It is recommended that lp_count/ilink1/ilink2 not be used as a dest reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)  * for memory load operations. If used in that way interrupts are deffered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)  * by hardware and that is not good.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)  *-------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .macro INTERRUPT_EPILOGUE  LVL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	POPAX	bta_l\LVL\()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	POPAX	lp_start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	POPAX	lp_end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	POP	r9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	mov	lp_count, r9	;LD to lp_count is not allowed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	POPAX	status32_l\LVL\()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	POP	ilink\LVL\()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	POP	blink
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	POP	fp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	POP	gp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	RESTORE_R12_TO_R0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #ifdef CONFIG_ARC_CURR_IN_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	ld	r25, [sp, 12]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	ld  sp, [sp] /* restore original sp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	/* orig_r0, ECR, user_r25 skipped automatically */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* Get thread_info of "current" tsk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .macro GET_CURR_THR_INFO_FROM_SP  reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	bic \reg, sp, (THREAD_SIZE - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* Get CPU-ID of this core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .macro  GET_CPU_ID  reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	lr  \reg, [identity]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	lsr \reg, \reg, 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	bmsk \reg, \reg, 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #endif  /* __ASM_ARC_ENTRY_COMPACT_H */