^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #ifndef __ASM_ARC_ENTRY_ARCV2_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #define __ASM_ARC_ENTRY_ARCV2_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <asm/asm-offsets.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <asm/dsp-impl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <asm/irqflags-arcv2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <asm/thread_info.h> /* For THREAD_SIZE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Interrupt/Exception stack layout (pt_regs) for ARCv2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * (End of struct aligned to end of page [unless nested])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * INTERRUPT EXCEPTION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * manual --------------------- manual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * | orig_r0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * | event/ECR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * | bta |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * | user_r25 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * | gp |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * | fp |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * | sp |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * | r12 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * | r30 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * | r58 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * | r59 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * hw autosave ---------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * optional | r0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * | r1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * ~ ~
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * | r9 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * | r10 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * | r11 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * | blink |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * | lpe |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * | lps |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * | lpc |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * | ei base |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * | ldi base |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * | jli base |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * ---------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * hw autosave | pc / eret |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * mandatory | stat32 / erstatus |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * ---------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /*------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .macro INTERRUPT_PROLOGUE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) ; (A) Before jumping to Interrupt Vector, hardware micro-ops did following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) ; 1. SP auto-switched to kernel mode stack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) ; 2. STATUS32.Z flag set if in U mode at time of interrupt (U:1,K:0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) ; 3. Auto save: (mandatory) Push PC and STAT32 on stack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) ; hardware does even if CONFIG_ARC_IRQ_NO_AUTOSAVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) ; 4. Auto save: (optional) r0-r11, blink, LPE,LPS,LPC, JLI,LDI,EI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) ; (B) Manually saved some regs: r12,r25,r30, sp,fp,gp, ACCL pair
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #ifdef CONFIG_ARC_IRQ_NO_AUTOSAVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) ; carve pt_regs on stack (case #3), PC/STAT32 already on stack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) sub sp, sp, SZ_PT_REGS - 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) __SAVE_REGFILE_HARD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) ; carve pt_regs on stack (case #4), which grew partially already
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) sub sp, sp, PT_r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) __SAVE_REGFILE_SOFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /*------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .macro EXCEPTION_PROLOGUE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) ; (A) Before jumping to Exception Vector, hardware micro-ops did following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) ; 1. SP auto-switched to kernel mode stack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ; 2. STATUS32.Z flag set if in U mode at time of exception (U:1,K:0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) ; (B) Manually save the complete reg file below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) sub sp, sp, SZ_PT_REGS ; carve pt_regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) ; _HARD saves r10 clobbered by _SOFT as scratch hence comes first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) __SAVE_REGFILE_HARD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) __SAVE_REGFILE_SOFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) st r0, [sp] ; orig_r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) lr r10, [eret]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) lr r11, [erstatus]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ST2 r10, r11, PT_ret
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) lr r10, [ecr]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) lr r11, [erbta]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) ST2 r10, r11, PT_event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ; OUTPUT: r10 has ECR expected by EV_Trap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /*------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * This macro saves the registers manually which would normally be autosaved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * by hardware on taken interrupts. It is used by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * - exception handlers (which don't have autosave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * - interrupt autosave disabled due to CONFIG_ARC_IRQ_NO_AUTOSAVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .macro __SAVE_REGFILE_HARD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ST2 r0, r1, PT_r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) ST2 r2, r3, PT_r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) ST2 r4, r5, PT_r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ST2 r6, r7, PT_r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) ST2 r8, r9, PT_r8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) ST2 r10, r11, PT_r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) st blink, [sp, PT_blink]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) lr r10, [lp_end]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) lr r11, [lp_start]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) ST2 r10, r11, PT_lpe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) st lp_count, [sp, PT_lpc]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ; skip JLI, LDI, EI for now
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /*------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * This macros saves a bunch of other registers which can't be autosaved for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * various reasons:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * - r12: the last caller saved scratch reg since hardware saves in pairs so r0-r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * - r30: free reg, used by gcc as scratch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * - ACCL/ACCH pair when they exist
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .macro __SAVE_REGFILE_SOFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ST2 gp, fp, PT_r26 ; gp (r26), fp (r27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) st r12, [sp, PT_sp + 4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) st r30, [sp, PT_sp + 8]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) ; Saving pt_regs->sp correctly requires some extra work due to the way
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) ; Auto stack switch works
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) ; - U mode: retrieve it from AUX_USER_SP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) ; - K mode: add the offset from current SP where H/w starts auto push
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) ; 1. Utilize the fact that Z bit is set if Intr taken in U mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ; 2. Upon entry SP is always saved (for any inspection, unwinding etc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) ; but on return, restored only if U mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) lr r10, [AUX_USER_SP] ; U mode SP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ; ISA requires ADD.nz to have same dest and src reg operands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) mov.nz r10, sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) add.nz r10, r10, SZ_PT_REGS ; K mode SP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) st r10, [sp, PT_sp] ; SP (pt_regs->sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #ifdef CONFIG_ARC_CURR_IN_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) st r25, [sp, PT_user_r25]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) GET_CURR_TASK_ON_CPU r25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #ifdef CONFIG_ARC_HAS_ACCL_REGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ST2 r58, r59, PT_r58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* clobbers r10, r11 registers pair */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) DSP_SAVE_REGFILE_IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /*------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .macro __RESTORE_REGFILE_SOFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) LD2 gp, fp, PT_r26 ; gp (r26), fp (r27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) ld r12, [sp, PT_r12]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) ld r30, [sp, PT_r30]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ; Restore SP (into AUX_USER_SP) only if returning to U mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ; - for K mode, it will be implicitly restored as stack is unwound
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ; - Z flag set on K is inverse of what hardware does on interrupt entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ; but that doesn't really matter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) bz 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) ld r10, [sp, PT_sp] ; SP (pt_regs->sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) sr r10, [AUX_USER_SP]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #ifdef CONFIG_ARC_CURR_IN_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) ld r25, [sp, PT_user_r25]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* clobbers r10, r11 registers pair */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) DSP_RESTORE_REGFILE_IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #ifdef CONFIG_ARC_HAS_ACCL_REGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) LD2 r58, r59, PT_r58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /*------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .macro __RESTORE_REGFILE_HARD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) ld blink, [sp, PT_blink]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) LD2 r10, r11, PT_lpe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) sr r10, [lp_end]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) sr r11, [lp_start]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) ld r10, [sp, PT_lpc] ; lp_count can't be target of LD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) mov lp_count, r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) LD2 r0, r1, PT_r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) LD2 r2, r3, PT_r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) LD2 r4, r5, PT_r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) LD2 r6, r7, PT_r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) LD2 r8, r9, PT_r8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) LD2 r10, r11, PT_r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /*------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .macro INTERRUPT_EPILOGUE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) ; INPUT: r0 has STAT32 of calling context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ; INPUT: Z flag set if returning to K mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ; _SOFT clobbers r10 restored by _HARD hence the order
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) __RESTORE_REGFILE_SOFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #ifdef CONFIG_ARC_IRQ_NO_AUTOSAVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) __RESTORE_REGFILE_HARD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) ; SP points to PC/STAT32: hw restores them despite NO_AUTOSAVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) add sp, sp, SZ_PT_REGS - 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) add sp, sp, PT_r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /*------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .macro EXCEPTION_EPILOGUE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ; INPUT: r0 has STAT32 of calling context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) btst r0, STATUS_U_BIT ; Z flag set if K, used in restoring SP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) ld r10, [sp, PT_event + 4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) sr r10, [erbta]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) LD2 r10, r11, PT_ret
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) sr r10, [eret]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) sr r11, [erstatus]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) __RESTORE_REGFILE_SOFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) __RESTORE_REGFILE_HARD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) add sp, sp, SZ_PT_REGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .macro FAKE_RET_FROM_EXCPN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) lr r9, [status32]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) bic r9, r9, STATUS_AE_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) or r9, r9, STATUS_IE_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) kflag r9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* Get thread_info of "current" tsk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .macro GET_CURR_THR_INFO_FROM_SP reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) bmskn \reg, sp, THREAD_SHIFT - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* Get CPU-ID of this core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .macro GET_CPU_ID reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) lr \reg, [identity]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) xbfu \reg, \reg, 0xE8 /* 00111 01000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* M = 8-1 N = 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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