^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * vineetg: May 2011: for Non-aliasing VIPT D-cache following can be NOPs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * -flush_cache_dup_mm (fork)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * -likewise for flush_cache_mm (exit/execve)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * -likewise for flush_cache_{range,page} (munmap, exit, COW-break)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * vineetg: April 2008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * -Added a critical CacheLine flush to copy_to_user_page( ) which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * was causing gdbserver to not setup breakpoints consistently
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #ifndef _ASM_CACHEFLUSH_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define _ASM_CACHEFLUSH_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/shmparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Semantically we need this because icache doesn't snoop dcache/dma.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * However ARC Cache flush requires paddr as well as vaddr, latter not available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * in the flush_icache_page() API. So we no-op it but do the equivalent work
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * in update_mmu_cache()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define flush_icache_page(vma, page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) void flush_cache_all(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) void flush_icache_range(unsigned long kstart, unsigned long kend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) void __sync_icache_dcache(phys_addr_t paddr, unsigned long vaddr, int len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) void __inv_icache_page(phys_addr_t paddr, unsigned long vaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) void __flush_dcache_page(phys_addr_t paddr, unsigned long vaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) void flush_dcache_page(struct page *page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) void dma_cache_wback_inv(phys_addr_t start, unsigned long sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) void dma_cache_inv(phys_addr_t start, unsigned long sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) void dma_cache_wback(phys_addr_t start, unsigned long sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define flush_dcache_mmap_lock(mapping) do { } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define flush_dcache_mmap_unlock(mapping) do { } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* TBD: optimize this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define flush_cache_vmap(start, end) flush_cache_all()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define flush_cache_vunmap(start, end) flush_cache_all()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define flush_cache_dup_mm(mm) /* called on fork (VIVT only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #ifndef CONFIG_ARC_CACHE_VIPT_ALIASING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define flush_cache_mm(mm) /* called on munmap/exit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define flush_cache_range(mm, u_vstart, u_vend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define flush_cache_page(vma, u_vaddr, pfn) /* PF handling/COW-break */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #else /* VIPT aliasing dcache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* To clear out stale userspace mappings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) void flush_cache_mm(struct mm_struct *mm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) void flush_cache_range(struct vm_area_struct *vma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned long start,unsigned long end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) void flush_cache_page(struct vm_area_struct *vma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) unsigned long user_addr, unsigned long page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * To make sure that userspace mapping is flushed to memory before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * get_user_pages() uses a kernel mapping to access the page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define ARCH_HAS_FLUSH_ANON_PAGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) void flush_anon_page(struct vm_area_struct *vma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct page *page, unsigned long u_vaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #endif /* CONFIG_ARC_CACHE_VIPT_ALIASING */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * A new pagecache page has PG_arch_1 clear - thus dcache dirty by default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * This works around some PIO based drivers which don't call flush_dcache_page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * to record that they dirtied the dcache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PG_dc_clean PG_arch_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CACHE_COLORS_NUM 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CACHE_COLORS_MSK (CACHE_COLORS_NUM - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CACHE_COLOR(addr) (((unsigned long)(addr) >> (PAGE_SHIFT)) & CACHE_COLORS_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * Simple wrapper over config option
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * Bootup code ensures that hardware matches kernel configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static inline int cache_is_vipt_aliasing(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return IS_ENABLED(CONFIG_ARC_CACHE_VIPT_ALIASING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * checks if two addresses (after page aligning) index into same cache set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define addr_not_cache_congruent(addr1, addr2) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) ({ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) cache_is_vipt_aliasing() ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) (CACHE_COLOR(addr1) != CACHE_COLOR(addr2)) : 0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define copy_to_user_page(vma, page, vaddr, dst, src, len) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) memcpy(dst, src, len); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (vma->vm_flags & VM_EXEC) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) __sync_icache_dcache((unsigned long)(dst), vaddr, len); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define copy_from_user_page(vma, page, vaddr, dst, src, len) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) memcpy(dst, src, len); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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