^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef __ARC_ASM_CACHE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define __ARC_ASM_CACHE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /* In case $$ not config, setup a dummy number for rest of kernel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef CONFIG_ARC_CACHE_LINE_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define L1_CACHE_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define L1_CACHE_SHIFT CONFIG_ARC_CACHE_LINE_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CACHE_LINE_MASK (~(L1_CACHE_BYTES - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * ARC700 doesn't cache any access in top 1G (0xc000_0000 to 0xFFFF_FFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Ideal for wiring memory mapped peripherals as we don't need to do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * explicit uncached accesses (LD.di/ST.di) hence more portable drivers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ARC_UNCACHED_ADDR_SPACE 0xc0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/build_bug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* Uncached access macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define arc_read_uncached_32(ptr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) ({ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) unsigned int __ret; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) __asm__ __volatile__( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) " ld.di %0, [%1] \n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) : "=r"(__ret) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) : "r"(ptr)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) __ret; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define arc_write_uncached_32(ptr, data)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) ({ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) __asm__ __volatile__( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) " st.di %0, [%1] \n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) : "r"(data), "r"(ptr)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* Largest line length for either L1 or L2 is 128 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SMP_CACHE_BYTES 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define cache_line_size() SMP_CACHE_BYTES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ARCH_DMA_MINALIGN SMP_CACHE_BYTES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * Make sure slab-allocated buffers are 64-bit aligned when atomic64_t uses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * ARCv2 64-bit atomics (LLOCKD/SCONDD). This guarantess runtime 64-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * alignment for any atomic64_t embedded in buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * Default ARCH_SLAB_MINALIGN is __alignof__(long long) which has a relaxed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * value of 4 (and not 8) in ARC ABI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #if defined(CONFIG_ARC_HAS_LL64) && defined(CONFIG_ARC_HAS_LLSC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define ARCH_SLAB_MINALIGN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) extern void arc_cache_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) extern char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) extern void read_decode_cache_bcr(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) extern int ioc_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) extern unsigned long perip_base, perip_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #endif /* !__ASSEMBLY__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* Instruction cache related Auxiliary registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define ARC_REG_IC_BCR 0x77 /* Build Config reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define ARC_REG_IC_IVIC 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define ARC_REG_IC_CTRL 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define ARC_REG_IC_IVIR 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define ARC_REG_IC_ENDR 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define ARC_REG_IC_IVIL 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define ARC_REG_IC_PTAG 0x1E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define ARC_REG_IC_PTAG_HI 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* Bit val in IC_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define IC_CTRL_DIS 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Data cache related Auxiliary registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define ARC_REG_DC_BCR 0x72 /* Build Config reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define ARC_REG_DC_IVDC 0x47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define ARC_REG_DC_CTRL 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define ARC_REG_DC_IVDL 0x4A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define ARC_REG_DC_FLSH 0x4B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define ARC_REG_DC_FLDL 0x4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define ARC_REG_DC_STARTR 0x4D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define ARC_REG_DC_ENDR 0x4E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define ARC_REG_DC_PTAG 0x5C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define ARC_REG_DC_PTAG_HI 0x5F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* Bit val in DC_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define DC_CTRL_DIS 0x001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define DC_CTRL_INV_MODE_FLUSH 0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define DC_CTRL_FLUSH_STATUS 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define DC_CTRL_RGN_OP_INV 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define DC_CTRL_RGN_OP_MSK 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /*System-level cache (L2 cache) related Auxiliary registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define ARC_REG_SLC_CFG 0x901
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define ARC_REG_SLC_CTRL 0x903
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define ARC_REG_SLC_FLUSH 0x904
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define ARC_REG_SLC_INVALIDATE 0x905
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define ARC_AUX_SLC_IVDL 0x910
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define ARC_AUX_SLC_FLDL 0x912
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define ARC_REG_SLC_RGN_START 0x914
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define ARC_REG_SLC_RGN_START1 0x915
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define ARC_REG_SLC_RGN_END 0x916
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define ARC_REG_SLC_RGN_END1 0x917
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* Bit val in SLC_CONTROL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SLC_CTRL_DIS 0x001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SLC_CTRL_IM 0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SLC_CTRL_BUSY 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SLC_CTRL_RGN_OP_INV 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* IO coherency related Auxiliary registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define ARC_REG_IO_COH_ENABLE 0x500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define ARC_IO_COH_ENABLE_BIT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define ARC_REG_IO_COH_PARTIAL 0x501
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define ARC_IO_COH_PARTIAL_BIT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define ARC_REG_IO_COH_AP0_BASE 0x508
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define ARC_REG_IO_COH_AP0_SIZE 0x509
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #endif /* _ASM_CACHE_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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