^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef _ASM_BITOPS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define _ASM_BITOPS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef _LINUX_BITOPS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #error only <linux/bitops.h> can be included directly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/compiler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/barrier.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #ifndef CONFIG_ARC_HAS_LLSC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #ifdef CONFIG_ARC_HAS_LLSC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Hardware assisted Atomic-R-M-W
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define BIT_OP(op, c_op, asm_op) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static inline void op##_bit(unsigned long nr, volatile unsigned long *m)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) unsigned int temp; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) m += nr >> 5; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) nr &= 0x1f; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) __asm__ __volatile__( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) "1: llock %0, [%1] \n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) " " #asm_op " %0, %0, %2 \n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) " scond %0, [%1] \n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) " bnz 1b \n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) : "=&r"(temp) /* Early clobber, to prevent reg reuse */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) : "r"(m), /* Not "m": llock only supports reg direct addr mode */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) "ir"(nr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) : "cc"); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * Semantically:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * Test the bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * if clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * set it and return 0 (old value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * return 1 (old value).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * Since ARC lacks a equivalent h/w primitive, the bit is set unconditionally
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * and the old value of bit is returned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define TEST_N_BIT_OP(op, c_op, asm_op) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static inline int test_and_##op##_bit(unsigned long nr, volatile unsigned long *m)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned long old, temp; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) m += nr >> 5; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) nr &= 0x1f; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * Explicit full memory barrier needed before/after as \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * LLOCK/SCOND themselves don't provide any such smenatic \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) smp_mb(); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) __asm__ __volatile__( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) "1: llock %0, [%2] \n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) " " #asm_op " %1, %0, %3 \n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) " scond %1, [%2] \n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) " bnz 1b \n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) : "=&r"(old), "=&r"(temp) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) : "r"(m), "ir"(nr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) : "cc"); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) smp_mb(); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return (old & (1 << nr)) != 0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #else /* !CONFIG_ARC_HAS_LLSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * Non hardware assisted Atomic-R-M-W
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * Locking would change to irq-disabling only (UP) and spinlocks (SMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * There's "significant" micro-optimization in writing our own variants of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * bitops (over generic variants)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * (1) The generic APIs have "signed" @nr while we have it "unsigned"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * This avoids extra code to be generated for pointer arithmatic, since
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * is "not sure" that index is NOT -ve
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * (2) Utilize the fact that ARCompact bit fidding insn (BSET/BCLR/ASL) etc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * only consider bottom 5 bits of @nr, so NO need to mask them off.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * (GCC Quirk: however for constant @nr we still need to do the masking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * at compile time)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define BIT_OP(op, c_op, asm_op) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static inline void op##_bit(unsigned long nr, volatile unsigned long *m)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) unsigned long temp, flags; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) m += nr >> 5; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * spin lock/unlock provide the needed smp_mb() before/after \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) bitops_lock(flags); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) temp = *m; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) *m = temp c_op (1UL << (nr & 0x1f)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) bitops_unlock(flags); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define TEST_N_BIT_OP(op, c_op, asm_op) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static inline int test_and_##op##_bit(unsigned long nr, volatile unsigned long *m)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) unsigned long old, flags; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) m += nr >> 5; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) bitops_lock(flags); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) old = *m; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) *m = old c_op (1UL << (nr & 0x1f)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) bitops_unlock(flags); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return (old & (1UL << (nr & 0x1f))) != 0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /***************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * Non atomic variants
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) **************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define __BIT_OP(op, c_op, asm_op) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static inline void __##op##_bit(unsigned long nr, volatile unsigned long *m) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) unsigned long temp; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) m += nr >> 5; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) temp = *m; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) *m = temp c_op (1UL << (nr & 0x1f)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define __TEST_N_BIT_OP(op, c_op, asm_op) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static inline int __test_and_##op##_bit(unsigned long nr, volatile unsigned long *m)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) unsigned long old; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) m += nr >> 5; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) old = *m; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) *m = old c_op (1UL << (nr & 0x1f)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return (old & (1UL << (nr & 0x1f))) != 0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define BIT_OPS(op, c_op, asm_op) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* set_bit(), clear_bit(), change_bit() */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) BIT_OP(op, c_op, asm_op) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* test_and_set_bit(), test_and_clear_bit(), test_and_change_bit() */\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) TEST_N_BIT_OP(op, c_op, asm_op) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* __set_bit(), __clear_bit(), __change_bit() */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) __BIT_OP(op, c_op, asm_op) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* __test_and_set_bit(), __test_and_clear_bit(), __test_and_change_bit() */\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) __TEST_N_BIT_OP(op, c_op, asm_op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) BIT_OPS(set, |, bset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) BIT_OPS(clear, & ~, bclr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) BIT_OPS(change, ^, bxor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * This routine doesn't need to be atomic.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) test_bit(unsigned int nr, const volatile unsigned long *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) unsigned long mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) addr += nr >> 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) mask = 1UL << (nr & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return ((mask & *addr) != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #ifdef CONFIG_ISA_ARCOMPACT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * Count the number of zeros, starting from MSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * Helper for fls( ) friends
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * This is a pure count, so (1-32) or (0-31) doesn't apply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * It could be 0 to 32, based on num of 0's in there
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * clz(0x8000_0000) = 0, clz(0xFFFF_FFFF)=0, clz(0) = 32, clz(1) = 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static inline __attribute__ ((const)) int clz(unsigned int x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) unsigned int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) __asm__ __volatile__(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) " norm.f %0, %1 \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) " mov.n %0, 0 \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) " add.p %0, %0, 1 \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) : "=r"(res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) : "r"(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) : "cc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static inline int constant_fls(unsigned int x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) int r = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (!x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (!(x & 0xffff0000u)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) x <<= 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) r -= 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (!(x & 0xff000000u)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) x <<= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) r -= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (!(x & 0xf0000000u)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) x <<= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) r -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (!(x & 0xc0000000u)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) x <<= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) r -= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (!(x & 0x80000000u))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) r -= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * fls = Find Last Set in word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * @result: [1-32]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * fls(1) = 1, fls(0x80000000) = 32, fls(0) = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static inline __attribute__ ((const)) int fls(unsigned int x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (__builtin_constant_p(x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return constant_fls(x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return 32 - clz(x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * __fls: Similar to fls, but zero based (0-31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static inline __attribute__ ((const)) int __fls(unsigned long x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (!x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return fls(x) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * ffs = Find First Set in word (LSB to MSB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * @result: [1-32], 0 if all 0's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define ffs(x) ({ unsigned long __t = (x); fls(__t & -__t); })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * __ffs: Similar to ffs, but zero based (0-31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static inline __attribute__ ((const)) unsigned long __ffs(unsigned long word)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (!word)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return ffs(word) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #else /* CONFIG_ISA_ARCV2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * fls = Find Last Set in word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * @result: [1-32]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * fls(1) = 1, fls(0x80000000) = 32, fls(0) = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static inline __attribute__ ((const)) int fls(unsigned long x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) int n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) asm volatile(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) " fls.f %0, %1 \n" /* 0:31; 0(Z) if src 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) " add.nz %0, %0, 1 \n" /* 0:31 -> 1:32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) : "=r"(n) /* Early clobber not needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) : "r"(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) : "cc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * __fls: Similar to fls, but zero based (0-31). Also 0 if no bit set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static inline __attribute__ ((const)) int __fls(unsigned long x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* FLS insn has exactly same semantics as the API */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return __builtin_arc_fls(x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * ffs = Find First Set in word (LSB to MSB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * @result: [1-32], 0 if all 0's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static inline __attribute__ ((const)) int ffs(unsigned long x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) int n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) asm volatile(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) " ffs.f %0, %1 \n" /* 0:31; 31(Z) if src 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) " add.nz %0, %0, 1 \n" /* 0:31 -> 1:32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) " mov.z %0, 0 \n" /* 31(Z)-> 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) : "=r"(n) /* Early clobber not needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) : "r"(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) : "cc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * __ffs: Similar to ffs, but zero based (0-31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static inline __attribute__ ((const)) unsigned long __ffs(unsigned long x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) unsigned long n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) asm volatile(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) " ffs.f %0, %1 \n" /* 0:31; 31(Z) if src 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) " mov.z %0, 0 \n" /* 31(Z)-> 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) : "=r"(n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) : "r"(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) : "cc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #endif /* CONFIG_ISA_ARCOMPACT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * ffz = Find First Zero in word.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * @return:[0-31], 32 if all 1's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define ffz(x) __ffs(~(x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #include <asm-generic/bitops/hweight.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #include <asm-generic/bitops/fls64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #include <asm-generic/bitops/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #include <asm-generic/bitops/lock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #include <asm-generic/bitops/find.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #include <asm-generic/bitops/le.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #include <asm-generic/bitops/ext2-atomic-setbit.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #endif /* !__ASSEMBLY__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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