^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef _ASM_ARC_ARCREGS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define _ASM_ARC_ARCREGS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /* Build Configuration Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define ARC_REG_AUX_DCCM 0x18 /* DCCM Base Addr ARCv2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define ARC_REG_ERP_CTRL 0x3F /* ARCv2 Error protection control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define ARC_REG_DCCM_BASE_BUILD 0x61 /* DCCM Base Addr ARCompact */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define ARC_REG_CRC_BCR 0x62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define ARC_REG_VECBASE_BCR 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define ARC_REG_PERIBASE_BCR 0x69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define ARC_REG_FP_BCR 0x6B /* ARCompact: Single-Precision FPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define ARC_REG_DPFP_BCR 0x6C /* ARCompact: Dbl Precision FPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define ARC_REG_ERP_BUILD 0xc7 /* ARCv2 Error protection Build: ECC/Parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define ARC_REG_FP_V2_BCR 0xc8 /* ARCv2 FPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define ARC_REG_SLC_BCR 0xce
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define ARC_REG_DCCM_BUILD 0x74 /* DCCM size (common) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define ARC_REG_AP_BCR 0x76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define ARC_REG_ICCM_BUILD 0x78 /* ICCM size (common) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ARC_REG_XY_MEM_BCR 0x79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ARC_REG_MAC_BCR 0x7a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ARC_REG_MUL_BCR 0x7b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ARC_REG_SWAP_BCR 0x7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ARC_REG_NORM_BCR 0x7d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ARC_REG_MIXMAX_BCR 0x7e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ARC_REG_BARREL_BCR 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ARC_REG_D_UNCACH_BCR 0x6A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ARC_REG_BPU_BCR 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ARC_REG_ISA_CFG_BCR 0xc1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ARC_REG_LPB_BUILD 0xE9 /* ARCv2 Loop Buffer Build */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ARC_REG_RTT_BCR 0xF2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ARC_REG_IRQ_BCR 0xF3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ARC_REG_MICRO_ARCH_BCR 0xF9 /* ARCv2 Product revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ARC_REG_SMART_BCR 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ARC_REG_CLUSTER_BCR 0xcf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ARC_REG_AUX_ICCM 0x208 /* ICCM Base Addr (ARCv2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ARC_REG_LPB_CTRL 0x488 /* ARCv2 Loop Buffer control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ARC_REG_FPU_CTRL 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define ARC_REG_FPU_STATUS 0x301
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* Common for ARCompact and ARCv2 status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ARC_REG_STATUS32 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* status32 Bits Positions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define STATUS_AE_BIT 5 /* Exception active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define STATUS_DE_BIT 6 /* PC is in delay slot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define STATUS_U_BIT 7 /* User/Kernel mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define STATUS_Z_BIT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define STATUS_L_BIT 12 /* Loop inhibit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* These masks correspond to the status word(STATUS_32) bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define STATUS_AE_MASK (1<<STATUS_AE_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define STATUS_DE_MASK (1<<STATUS_DE_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define STATUS_U_MASK (1<<STATUS_U_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define STATUS_Z_MASK (1<<STATUS_Z_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define STATUS_L_MASK (1<<STATUS_L_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * ECR: Exception Cause Reg bits-n-pieces
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * [23:16] = Exception Vector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * [15: 8] = Exception Cause Code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * [ 7: 0] = Exception Parameters (for certain types only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #ifdef CONFIG_ISA_ARCOMPACT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define ECR_V_MEM_ERR 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define ECR_V_INSN_ERR 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define ECR_V_MACH_CHK 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define ECR_V_ITLB_MISS 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define ECR_V_DTLB_MISS 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define ECR_V_PROTV 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define ECR_V_TRAP 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define ECR_V_MEM_ERR 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define ECR_V_INSN_ERR 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define ECR_V_MACH_CHK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define ECR_V_ITLB_MISS 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define ECR_V_DTLB_MISS 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define ECR_V_PROTV 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define ECR_V_TRAP 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define ECR_V_MISALIGN 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* DTLB Miss and Protection Violation Cause Codes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define ECR_C_PROTV_INST_FETCH 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define ECR_C_PROTV_LOAD 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define ECR_C_PROTV_STORE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define ECR_C_PROTV_XCHG 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define ECR_C_PROTV_MISALIG_DATA 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define ECR_C_BIT_PROTV_MISALIG_DATA 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* Machine Check Cause Code Values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define ECR_C_MCHK_DUP_TLB 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* DTLB Miss Exception Cause Code Values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define ECR_C_BIT_DTLB_LD_MISS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define ECR_C_BIT_DTLB_ST_MISS 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* Auxiliary registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define AUX_IDENTITY 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define AUX_EXEC_CTRL 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define AUX_INTR_VEC_BASE 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define AUX_VOL 0x5e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * Floating Pt Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * Status regs are read-only (build-time) so need not be saved/restored
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define ARC_AUX_FP_STAT 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define ARC_AUX_DPFP_1L 0x301
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define ARC_AUX_DPFP_1H 0x302
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define ARC_AUX_DPFP_2L 0x303
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define ARC_AUX_DPFP_2H 0x304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define ARC_AUX_DPFP_STAT 0x305
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * DSP-related registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * Registers names must correspond to dsp_callee_regs structure fields names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * for automatic offset calculation in DSP_AUX_SAVE_RESTORE macros.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define ARC_AUX_DSP_BUILD 0x7A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define ARC_AUX_ACC0_LO 0x580
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define ARC_AUX_ACC0_GLO 0x581
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define ARC_AUX_ACC0_HI 0x582
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define ARC_AUX_ACC0_GHI 0x583
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define ARC_AUX_DSP_BFLY0 0x598
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define ARC_AUX_DSP_CTRL 0x59F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define ARC_AUX_DSP_FFT_CTRL 0x59E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define ARC_AUX_AGU_BUILD 0xCC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define ARC_AUX_AGU_AP0 0x5C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define ARC_AUX_AGU_AP1 0x5C1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define ARC_AUX_AGU_AP2 0x5C2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define ARC_AUX_AGU_AP3 0x5C3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define ARC_AUX_AGU_OS0 0x5D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define ARC_AUX_AGU_OS1 0x5D1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define ARC_AUX_AGU_MOD0 0x5E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define ARC_AUX_AGU_MOD1 0x5E1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define ARC_AUX_AGU_MOD2 0x5E2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define ARC_AUX_AGU_MOD3 0x5E3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #include <soc/arc/aux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* Helpers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define TO_KB(bytes) ((bytes) >> 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define TO_MB(bytes) (TO_KB(bytes) >> 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define PAGES_TO_KB(n_pages) ((n_pages) << (PAGE_SHIFT - 10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define PAGES_TO_MB(n_pages) (PAGES_TO_KB(n_pages) >> 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ***************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * Build Configuration Registers, with encoded hardware config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct bcr_identity {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #ifdef CONFIG_CPU_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) unsigned int chip_id:16, cpu_id:8, family:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned int family:8, cpu_id:8, chip_id:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct bcr_isa_arcv2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #ifdef CONFIG_CPU_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) unsigned int div_rem:4, pad2:4, ldd:1, unalign:1, atomic:1, be:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) pad1:12, ver:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) unsigned int ver:8, pad1:12, be:1, atomic:1, unalign:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) ldd:1, pad2:4, div_rem:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct bcr_uarch_build_arcv2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #ifdef CONFIG_CPU_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) unsigned int pad:8, prod:8, maj:8, min:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) unsigned int min:8, maj:8, prod:8, pad:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct bcr_mpy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #ifdef CONFIG_CPU_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) unsigned int pad:8, x1616:8, dsp:4, cycles:2, type:2, ver:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) unsigned int ver:8, type:2, cycles:2, dsp:4, x1616:8, pad:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct bcr_iccm_arcompact {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #ifdef CONFIG_CPU_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) unsigned int base:16, pad:5, sz:3, ver:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) unsigned int ver:8, sz:3, pad:5, base:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct bcr_iccm_arcv2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #ifdef CONFIG_CPU_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) unsigned int pad:8, sz11:4, sz01:4, sz10:4, sz00:4, ver:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) unsigned int ver:8, sz00:4, sz10:4, sz01:4, sz11:4, pad:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct bcr_dccm_arcompact {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #ifdef CONFIG_CPU_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) unsigned int res:21, sz:3, ver:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) unsigned int ver:8, sz:3, res:21;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct bcr_dccm_arcv2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #ifdef CONFIG_CPU_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) unsigned int pad2:12, cyc:3, pad1:1, sz1:4, sz0:4, ver:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) unsigned int ver:8, sz0:4, sz1:4, pad1:1, cyc:3, pad2:12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* ARCompact: Both SP and DP FPU BCRs have same format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct bcr_fp_arcompact {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #ifdef CONFIG_CPU_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) unsigned int fast:1, ver:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) unsigned int ver:8, fast:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct bcr_fp_arcv2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #ifdef CONFIG_CPU_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) unsigned int pad2:15, dp:1, pad1:7, sp:1, ver:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) unsigned int ver:8, sp:1, pad1:7, dp:1, pad2:15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct bcr_actionpoint {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #ifdef CONFIG_CPU_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) unsigned int pad:21, min:1, num:2, ver:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) unsigned int ver:8, num:2, min:1, pad:21;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #include <soc/arc/timers.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct bcr_bpu_arcompact {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #ifdef CONFIG_CPU_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) unsigned int pad2:19, fam:1, pad:2, ent:2, ver:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) unsigned int ver:8, ent:2, pad:2, fam:1, pad2:19;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct bcr_bpu_arcv2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #ifdef CONFIG_CPU_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) unsigned int pad:6, fbe:2, tqe:2, ts:4, ft:1, rse:2, pte:3, bce:3, ver:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) unsigned int ver:8, bce:3, pte:3, rse:2, ft:1, ts:4, tqe:2, fbe:2, pad:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* Error Protection Build: ECC/Parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct bcr_erp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #ifdef CONFIG_CPU_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) unsigned int pad3:5, mmu:3, pad2:4, ic:3, dc:3, pad1:6, ver:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) unsigned int ver:8, pad1:6, dc:3, ic:3, pad2:4, mmu:3, pad3:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* Error Protection Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct ctl_erp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #ifdef CONFIG_CPU_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) unsigned int pad2:27, mpd:1, pad1:2, dpd:1, dpi:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) unsigned int dpi:1, dpd:1, pad1:2, mpd:1, pad2:27;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct bcr_lpb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #ifdef CONFIG_CPU_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) unsigned int pad:16, entries:8, ver:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) unsigned int ver:8, entries:8, pad:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct bcr_generic {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #ifdef CONFIG_CPU_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) unsigned int info:24, ver:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) unsigned int ver:8, info:24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) *******************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * Generic structures to hold build configuration used at runtime
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) struct cpuinfo_arc_mmu {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) unsigned int ver:4, pg_sz_k:8, s_pg_sz_m:8, pad:10, sasid:1, pae:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) unsigned int sets:12, ways:4, u_dtlb:8, u_itlb:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct cpuinfo_arc_cache {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) unsigned int sz_k:14, line_len:8, assoc:4, alias:1, vipt:1, pad:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct cpuinfo_arc_bpu {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) unsigned int ver, full, num_cache, num_pred, ret_stk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct cpuinfo_arc_ccm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) unsigned int base_addr, sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct cpuinfo_arc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct cpuinfo_arc_cache icache, dcache, slc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) struct cpuinfo_arc_mmu mmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct cpuinfo_arc_bpu bpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct bcr_identity core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct bcr_isa_arcv2 isa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) const char *release, *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) unsigned int vec_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct cpuinfo_arc_ccm iccm, dccm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) unsigned int swap:1, norm:1, minmax:1, barrel:1, crc:1, swape:1, pad1:2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) fpu_sp:1, fpu_dp:1, dual:1, dual_enb:1, pad2:4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) ap_num:4, ap_full:1, smart:1, rtt:1, pad3:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) timer0:1, timer1:1, rtc:1, gfrc:1, pad4:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) } extn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) struct bcr_mpy extn_mpy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) extern struct cpuinfo_arc cpuinfo_arc700[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static inline int is_isa_arcv2(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return IS_ENABLED(CONFIG_ISA_ARCV2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static inline int is_isa_arcompact(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return IS_ENABLED(CONFIG_ISA_ARCOMPACT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #endif /* __ASEMBLY__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #endif /* _ASM_ARC_ARCREGS_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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