Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 2012 Synopsys, Inc. (www.synopsys.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Skeleton device tree; the bare minimum needed to boot; just include and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * add a compatible value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) / {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 	compatible = "snps,arc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	#size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	chosen { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	aliases { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	cpus {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 		#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 		#size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 		cpu@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 			device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 			compatible = "snps,arc770d";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 			reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 			clocks = <&core_clk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	/* TIMER0 with interrupt for clockevent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	timer0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		compatible = "snps,arc-timer";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		interrupts = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		interrupt-parent = <&core_intc>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		clocks = <&core_clk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	/* TIMER1 for free running clocksource */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	timer1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		compatible = "snps,arc-timer";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		clocks = <&core_clk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	memory {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		device_type = "memory";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		reg = <0x80000000 0x10000000>;	/* 256M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };