Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) /dts-v1/;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) /include/ "skeleton.dtsi"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) / {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 	model = "snps,nsimosci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 	compatible = "snps,nsimosci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 	#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	#size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	interrupt-parent = <&core_intc>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	chosen {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 		/* this is for console on PGU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 		/* bootargs = "console=tty0 consoleblank=0"; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 		/* this is for console on serial */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 		bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblank=0 debug video=640x480-24 print-fatal-signals=1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	aliases {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 		serial0 = &uart0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	fpga {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		compatible = "simple-bus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		#size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		/* child and parent address space 1:1 mapped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		core_clk: core_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 			#clock-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 			compatible = "fixed-clock";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 			clock-frequency = <20000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		core_intc: interrupt-controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 			compatible = "snps,arc700-intc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 			interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 			#interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		uart0: serial@f0000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 			compatible = "ns8250";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 			reg = <0xf0000000 0x2000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 			interrupts = <11>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 			clock-frequency = <3686400>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 			baud = <115200>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 			reg-shift = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 			reg-io-width = <4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 			no-loopback-test = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 		pguclk: pguclk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 			#clock-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 			compatible = "fixed-clock";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 			clock-frequency = <25175000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 		pgu@f9000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 			compatible = "snps,arcpgu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 			reg = <0xf9000000 0x400>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 			clocks = <&pguclk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 			clock-names = "pxlclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 		ps2: ps2@f9001000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 			compatible = "snps,arc_ps2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 			reg = <0xf9000400 0x14>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 			interrupts = <13>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 			interrupt-names = "arc_ps2_irq";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 		eth0: ethernet@f0003000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 			compatible = "ezchip,nps-mgt-enet";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 			reg = <0xf0003000 0x44>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 			interrupts = <7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 		arcpct0: pct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 			compatible = "snps,arc700-pct";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };