Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Device Tree for ARC HS Development Kit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) /dts-v1/;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <dt-bindings/gpio/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <dt-bindings/reset/snps,hsdk-reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) / {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 	model = "snps,hsdk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 	compatible = "snps,hsdk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 	#address-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	#size-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	chosen {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 		bootargs = "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	aliases {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 		ethernet = &gmac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	cpus {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 		#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 		#size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 		cpu@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 			device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 			compatible = "snps,archs38";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 			reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 			clocks = <&core_clk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		cpu@1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 			device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 			compatible = "snps,archs38";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 			reg = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 			clocks = <&core_clk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		cpu@2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 			device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 			compatible = "snps,archs38";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 			reg = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 			clocks = <&core_clk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		cpu@3 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 			device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 			compatible = "snps,archs38";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 			reg = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 			clocks = <&core_clk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	input_clk: input-clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		#clock-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		compatible = "fixed-clock";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		clock-frequency = <33333333>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	reg_5v0: regulator-5v0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		compatible = "regulator-fixed";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		regulator-name = "5v0-supply";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		regulator-min-microvolt = <5000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		regulator-max-microvolt = <5000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	cpu_intc: cpu-interrupt-controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		compatible = "snps,archs-intc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		#interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	idu_intc: idu-interrupt-controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		compatible = "snps,archs-idu-intc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		#interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		interrupt-parent = <&cpu_intc>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	arcpct: pct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		compatible = "snps,archs-pct";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		interrupt-parent = <&cpu_intc>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		interrupts = <20>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	/* TIMER0 with interrupt for clockevent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	timer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		compatible = "snps,arc-timer";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		interrupts = <16>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		interrupt-parent = <&cpu_intc>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		clocks = <&core_clk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	/* 64-bit Global Free Running Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	gfrc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		compatible = "snps,archs-timer-gfrc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		clocks = <&core_clk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	soc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		compatible = "simple-bus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		#size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		interrupt-parent = <&idu_intc>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		cgu_rst: reset-controller@8a0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 			compatible = "snps,hsdk-reset";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 			#reset-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 			reg = <0x8a0 0x4>, <0xff0 0x4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		core_clk: core-clk@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 			compatible = "snps,hsdk-core-pll-clock";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 			reg = <0x00 0x10>, <0x14b8 0x4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 			#clock-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 			clocks = <&input_clk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 			/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 			 * Set initial core pll output frequency to 1GHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 			 * It will be applied at the core pll driver probing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 			 * on early boot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 			assigned-clocks = <&core_clk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 			assigned-clock-rates = <1000000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		serial: serial@5000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 			compatible = "snps,dw-apb-uart";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 			reg = <0x5000 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 			clock-frequency = <33330000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 			interrupts = <6>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 			baud = <115200>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 			reg-shift = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 			reg-io-width = <4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		gmacclk: gmacclk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 			compatible = "fixed-clock";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 			clock-frequency = <400000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 			#clock-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		mmcclk_ciu: mmcclk-ciu {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 			compatible = "fixed-clock";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 			/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 			 * DW sdio controller has external ciu clock divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 			 * controlled via register in SDIO IP. Due to its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 			 * unexpected default value (it should divide by 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 			 * but it divides by 8) SDIO IP uses wrong clock and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 			 * works unstable (see STAR 9001204800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 			 * We switched to the minimum possible value of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 			 * divisor (div-by-2) in HSDK platform code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 			 * So add temporary fix and change clock frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 			 * to 50000000 Hz until we fix dw sdio driver itself.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 			clock-frequency = <50000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 			#clock-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		mmcclk_biu: mmcclk-biu {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 			compatible = "fixed-clock";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 			clock-frequency = <400000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 			#clock-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		gpu_core_clk: gpu-core-clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 			compatible = "fixed-clock";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 			clock-frequency = <400000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 			#clock-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		gpu_dma_clk: gpu-dma-clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 			compatible = "fixed-clock";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 			clock-frequency = <400000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 			#clock-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		gpu_cfg_clk: gpu-cfg-clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 			compatible = "fixed-clock";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 			clock-frequency = <200000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 			#clock-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		dmac_core_clk: dmac-core-clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 			compatible = "fixed-clock";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 			clock-frequency = <400000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 			#clock-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		dmac_cfg_clk: dmac-gpu-cfg-clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 			compatible = "fixed-clock";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 			clock-frequency = <200000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 			#clock-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		gmac: ethernet@8000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 			#interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 			compatible = "snps,dwmac";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 			reg = <0x8000 0x2000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 			interrupts = <10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 			interrupt-names = "macirq";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 			phy-mode = "rgmii-id";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 			snps,pbl = <32>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 			snps,multicast-filter-bins = <256>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 			clocks = <&gmacclk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 			clock-names = "stmmaceth";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 			phy-handle = <&phy0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 			resets = <&cgu_rst HSDK_ETH_RESET>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 			reset-names = "stmmaceth";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 			mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 			dma-coherent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 			tx-fifo-depth = <4096>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 			rx-fifo-depth = <4096>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 			mdio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 				#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 				#size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 				compatible = "snps,dwmac-mdio";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 				phy0: ethernet-phy@0 { /* Micrel KSZ9031 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 					reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 				};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 			};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		ohci@60000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 			compatible = "snps,hsdk-v1.0-ohci", "generic-ohci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 			reg = <0x60000 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 			interrupts = <15>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 			resets = <&cgu_rst HSDK_USB_RESET>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 			dma-coherent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		ehci@40000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 			compatible = "snps,hsdk-v1.0-ehci", "generic-ehci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 			reg = <0x40000 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 			interrupts = <15>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 			resets = <&cgu_rst HSDK_USB_RESET>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 			dma-coherent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		mmc@a000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 			compatible = "altr,socfpga-dw-mshc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 			reg = <0xa000 0x400>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 			num-slots = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 			fifo-depth = <16>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 			card-detect-delay = <200>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 			clocks = <&mmcclk_biu>, <&mmcclk_ciu>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 			clock-names = "biu", "ciu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 			interrupts = <12>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 			bus-width = <4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 			dma-coherent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		spi0: spi@20000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 			compatible = "snps,dw-apb-ssi";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 			reg = <0x20000 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 			#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 			#size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 			interrupts = <16>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 			num-cs = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 			reg-io-width = <4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 			clocks = <&input_clk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 			cs-gpios = <&creg_gpio 0 GPIO_ACTIVE_LOW>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 				   <&creg_gpio 1 GPIO_ACTIVE_LOW>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 			spi-flash@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 				compatible = "sst26wf016b", "jedec,spi-nor";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 				reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 				#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 				#size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 				spi-max-frequency = <4000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 			};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 			adc@1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 				compatible = "ti,adc108s102";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 				reg = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 				vref-supply = <&reg_5v0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 				spi-max-frequency = <1000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 			};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		creg_gpio: gpio@14b0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 			compatible = "snps,creg-gpio-hsdk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 			reg = <0x14b0 0x4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 			gpio-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 			#gpio-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 			ngpios = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		gpio: gpio@3000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 			compatible = "snps,dw-apb-gpio";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 			reg = <0x3000 0x20>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 			#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 			#size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 			gpio_port_a: gpio-controller@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 				compatible = "snps,dw-apb-gpio-port";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 				gpio-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 				#gpio-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 				snps,nr-gpios = <24>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 				reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 			};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		gpu_3d: gpu@90000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 			compatible = "vivante,gc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 			reg = <0x90000 0x4000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 			clocks = <&gpu_dma_clk>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 				 <&gpu_cfg_clk>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 				 <&gpu_core_clk>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 				 <&gpu_core_clk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 			clock-names = "bus", "reg", "core", "shader";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 			interrupts = <28>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		dmac: dmac@80000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 			compatible = "snps,axi-dma-1.01a";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 			reg = <0x80000 0x400>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 			interrupts = <27>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 			clocks = <&dmac_core_clk>, <&dmac_cfg_clk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 			clock-names = "core-clk", "cfgr-clk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 			dma-channels = <4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 			snps,dma-masters = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 			snps,data-width = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 			snps,block-size = <4096 4096 4096 4096>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 			snps,priority = <0 1 2 3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 			snps,axi-max-burst-len = <16>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	memory@80000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		#address-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		#size-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		device_type = "memory";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		reg = <0x0 0x80000000 0x0 0x40000000>;  /* 1 GB lowmem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		/*     0x1 0x00000000 0x0 0x40000000>;     1 GB highmem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) };