^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Device tree for AXC003 CPU card: HS38x UP configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /include/ "skeleton_hs.dtsi"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) / {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) compatible = "snps,arc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #address-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #size-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) cpu_card {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) compatible = "simple-bus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) input_clk: input-clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #clock-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) compatible = "fixed-clock";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) clock-frequency = <33333333>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) core_clk: core-clk@80 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) compatible = "snps,axs10x-arc-pll-clock";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) reg = <0x80 0x10>, <0x100 0x10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #clock-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) clocks = <&input_clk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * Set initial core pll output frequency to 90MHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * It will be applied at the core pll driver probing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * on early boot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) assigned-clocks = <&core_clk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) assigned-clock-rates = <90000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) core_intc: archs-intc@cpu {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) compatible = "snps,archs-intc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * this GPIO block ORs all interrupts on CPU card (creg,..)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * to uplink only 1 IRQ to ARC core intc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) dw-apb-gpio@2000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) compatible = "snps,dw-apb-gpio";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) reg = < 0x2000 0x80 >;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) ictl_intc: gpio-controller@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) compatible = "snps,dw-apb-gpio-port";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) gpio-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #gpio-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) snps,nr-gpios = <30>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #interrupt-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) interrupt-parent = <&core_intc>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) interrupts = <25>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) debug_uart: dw-apb-uart@5000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) compatible = "snps,dw-apb-uart";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) reg = <0x5000 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) clock-frequency = <33333000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) interrupt-parent = <&ictl_intc>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) interrupts = <2 4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) baud = <115200>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) reg-shift = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) reg-io-width = <4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) arcpct0: pct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) compatible = "snps,archs-pct";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) interrupt-parent = <&core_intc>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) interrupts = <20>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * Mark DMA peripherals connected via IOC port as dma-coherent. We do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * it via overlay because peripherals defined in axs10x_mb.dtsi are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * used for both AXS101 and AXS103 boards and only AXS103 has IOC (so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * only AXS103 board has HW-coherent DMA peripherals)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * We don't need to mark pgu@17000 as dma-coherent because it uses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * external DMA buffer located outside of IOC aperture.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) axs10x_mb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) ethernet@18000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) dma-coherent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) ehci@40000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) dma-coherent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ohci@60000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) dma-coherent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) mmc@15000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) dma-coherent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * The DW APB ICTL intc on MB is connected to CPU intc via a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * DT "invisible" DW APB GPIO block, configured to simply pass thru
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * interrupts - setup accordinly in platform init (plat-axs10x/ax10x.c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * So here we mimic a direct connection betwen them, ignoring the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * ABPG GPIO. Thus set "interrupts = <24>" (DW APB GPIO to core)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * instead of "interrupts = <12>" (DW APB ICTL to DW APB GPIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * This intc actually resides on MB, but we move it here to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * avoid duplicating the MB dtsi file given that IRQ from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * this intc to cpu intc are different for axs101 and axs103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) mb_intc: interrupt-controller@e0012000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) compatible = "snps,dw-apb-ictl";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) reg = < 0x0 0xe0012000 0x0 0x200 >;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) interrupt-parent = <&core_intc>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) interrupts = < 24 >;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) memory {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) device_type = "memory";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* CONFIG_LINUX_RAM_BASE needs to match low mem start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) reg = <0x0 0x80000000 0x0 0x20000000 /* 512 MiB low mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 0x1 0xc0000000 0x0 0x40000000>; /* 1 GiB highmem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) reserved-memory {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #address-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #size-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * Move frame buffer out of IOC aperture (0x8z-0xaz).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) frame_buffer: frame_buffer@be000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) compatible = "shared-dma-pool";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) reg = <0x0 0xbe000000 0x0 0x2000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) no-map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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