^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Device tree for AXC001 770D/EM6/AS221 CPU card
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Note that this file only supports the 770D CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /include/ "skeleton.dtsi"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) / {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) compatible = "snps,arc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #address-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #size-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) cpu_card {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) compatible = "simple-bus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) core_clk: core_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #clock-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) compatible = "fixed-clock";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) clock-frequency = <750000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) input_clk: input-clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #clock-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) compatible = "fixed-clock";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) clock-frequency = <33333333>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) core_intc: arc700-intc@cpu {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) compatible = "snps,arc700-intc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * this GPIO block ORs all interrupts on CPU card (creg,..)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * to uplink only 1 IRQ to ARC core intc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) dw-apb-gpio@2000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) compatible = "snps,dw-apb-gpio";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) reg = < 0x2000 0x80 >;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) ictl_intc: gpio-controller@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) compatible = "snps,dw-apb-gpio-port";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) gpio-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #gpio-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) snps,nr-gpios = <30>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #interrupt-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) interrupt-parent = <&core_intc>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) interrupts = <15>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) debug_uart: dw-apb-uart@5000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) compatible = "snps,dw-apb-uart";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) reg = <0x5000 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) clock-frequency = <33333000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) interrupt-parent = <&ictl_intc>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) interrupts = <19 4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) baud = <115200>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) reg-shift = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) reg-io-width = <4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) arcpct0: pct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) compatible = "snps,arc700-pct";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * This INTC is actually connected to DW APB GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * which acts as a wire between MB INTC and CPU INTC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * GPIO INTC is configured in platform init code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * and here we mimic direct connection from MB INTC to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * CPU INTC, thus we set "interrupts = <7>" instead of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * "interrupts = <12>"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * This intc actually resides on MB, but we move it here to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * avoid duplicating the MB dtsi file given that IRQ from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * this intc to cpu intc are different for axs101 and axs103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) mb_intc: interrupt-controller@e0012000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) compatible = "snps,dw-apb-ictl";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) reg = < 0x0 0xe0012000 0x0 0x200 >;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) interrupt-parent = <&core_intc>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) interrupts = < 7 >;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) memory {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) device_type = "memory";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* CONFIG_LINUX_RAM_BASE needs to match low mem start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) reg = <0x0 0x80000000 0x0 0x1b000000>; /* (512 - 32) MiB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) reserved-memory {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #address-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #size-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * We just move frame buffer area to the very end of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * available DDR. And even though in case of ARC770 there's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * no strict requirement for a frame-buffer to be in any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * particular location it allows us to use the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * base board's DT node for ARC PGU as for ARc HS38.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) frame_buffer: frame_buffer@9e000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) compatible = "shared-dma-pool";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) reg = <0x0 0x9e000000 0x0 0x2000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) no-map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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