^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) # SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) config ARC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) def_bool y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) select ARC_TIMERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) select ARCH_HAS_DEBUG_VM_PGTABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) select ARCH_HAS_DMA_PREP_COHERENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) select ARCH_HAS_PTE_SPECIAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) select ARCH_HAS_SETUP_DMA_OPS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) select ARCH_HAS_SYNC_DMA_FOR_CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) select ARCH_HAS_SYNC_DMA_FOR_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) select ARCH_32BIT_OFF_T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) select BUILDTIME_TABLE_SORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) select CLONE_BACKWARDS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) select COMMON_CLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) select DMA_DIRECT_REMAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) select GENERIC_CLOCKEVENTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) select GENERIC_FIND_FIRST_BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) select GENERIC_IRQ_SHOW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) select GENERIC_PCI_IOMAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) select GENERIC_PENDING_IRQ if SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) select GENERIC_SCHED_CLOCK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) select GENERIC_SMP_IDLE_THREAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) select HAVE_ARCH_KGDB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) select HAVE_ARCH_TRACEHOOK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) select HAVE_DEBUG_STACKOVERFLOW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) select HAVE_DEBUG_KMEMLEAK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) select HAVE_FUTEX_CMPXCHG if FUTEX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) select HAVE_IOREMAP_PROT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) select HAVE_KERNEL_GZIP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) select HAVE_KERNEL_LZMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) select HAVE_KPROBES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) select HAVE_KRETPROBES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) select HAVE_MOD_ARCH_SPECIFIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) select HAVE_OPROFILE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) select HAVE_PERF_EVENTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) select HANDLE_DOMAIN_IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) select IRQ_DOMAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) select MODULES_USE_ELF_RELA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) select OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) select OF_EARLY_FLATTREE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) select PCI_SYSCALL if PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) select PERF_USE_VMALLOC if ARC_CACHE_VIPT_ALIASING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) select HAVE_ARCH_JUMP_LABEL if ISA_ARCV2 && !CPU_ENDIAN_BE32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) select SET_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) config ARCH_HAS_CACHE_LINE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) def_bool y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) config TRACE_IRQFLAGS_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) def_bool y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) config LOCKDEP_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) def_bool y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) config SCHED_OMIT_FRAME_POINTER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) def_bool y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) config GENERIC_CSUM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) def_bool y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) config ARCH_DISCONTIGMEM_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) def_bool n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) config ARCH_FLATMEM_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) def_bool y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) config MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) def_bool y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) config NO_IOPORT_MAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) def_bool y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) config GENERIC_CALIBRATE_DELAY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) def_bool y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) config GENERIC_HWEIGHT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) def_bool y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) config STACKTRACE_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) def_bool y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) select STACKTRACE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) config HAVE_ARCH_TRANSPARENT_HUGEPAGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) def_bool y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) depends on ARC_MMU_V4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) menu "ARC Architecture Configuration"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) menu "ARC Platform/SoC/Board"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) source "arch/arc/plat-tb10x/Kconfig"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) source "arch/arc/plat-axs10x/Kconfig"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) source "arch/arc/plat-hsdk/Kconfig"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) endmenu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) choice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) prompt "ARC Instruction Set"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) default ISA_ARCV2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) config ISA_ARCOMPACT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) bool "ARCompact ISA"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) select CPU_NO_EFFICIENT_FFS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) The original ARC ISA of ARC600/700 cores
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) config ISA_ARCV2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) bool "ARC ISA v2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) select ARC_TIMERS_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) ISA for the Next Generation ARC-HS cores
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) endchoice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) menu "ARC CPU Configuration"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) choice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) prompt "ARC Core"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) default ARC_CPU_770 if ISA_ARCOMPACT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) default ARC_CPU_HS if ISA_ARCV2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if ISA_ARCOMPACT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) config ARC_CPU_750D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) bool "ARC750D"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) select ARC_CANT_LLSC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) Support for ARC750 core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) config ARC_CPU_770
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) bool "ARC770"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) select ARC_HAS_SWAPE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) Support for ARC770 core introduced with Rel 4.10 (Summer 2011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) This core has a bunch of cool new features:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) Shared Address Spaces (for sharing TLB entries in MMU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) -Caches: New Prog Model, Region Flush
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) endif #ISA_ARCOMPACT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) config ARC_CPU_HS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) bool "ARC-HS"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) depends on ISA_ARCV2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) Support for ARC HS38x Cores based on ARCv2 ISA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) The notable features are:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) - SMP configurations of up to 4 cores with coherency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) - Optional L2 Cache and IO-Coherency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) - Revised Interrupt Architecture (multiple priorites, reg banks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) auto stack switch, auto regfile save/restore)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) - MMUv4 (PIPT dcache, Huge Pages)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) - Instructions for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * 64bit load/store: LDD, STD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * Hardware assisted divide/remainder: DIV, REM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * Function prologue/epilogue: ENTER_S, LEAVE_S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * IRQ enable/disable: CLRI, SETI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * pop count: FFS, FLS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * SETcc, BMSKN, XBFU...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) endchoice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) config ARC_TUNE_MCPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) string "Override default -mcpu compiler flag"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) default ""
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) Override default -mcpu=xxx compiler flag (which is set depending on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) the ISA version) with the specified value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) NOTE: If specified flag isn't supported by current compiler the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) ISA default value will be used as a fallback.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) config CPU_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) bool "Enable Big Endian Mode"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) Build kernel for Big Endian Mode of ARC CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) config SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) bool "Symmetric Multi-Processing"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) select ARC_MCIP if ISA_ARCV2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) This enables support for systems with more than one CPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) config NR_CPUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) int "Maximum number of CPUs (2-4096)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) range 2 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) default "4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) config ARC_SMP_HALT_ON_RESET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) bool "Enable Halt-on-reset boot mode"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) In SMP configuration cores can be configured as Halt-on-reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) or they could all start at same time. For Halt-on-reset, non
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) masters are parked until Master kicks them so they can start off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) at designated entry point. For other case, all jump to common
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) entry point and spin wait for Master's signal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) endif #SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) config ARC_MCIP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) bool "ARConnect Multicore IP (MCIP) Support "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) depends on ISA_ARCV2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) default y if SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) This IP block enables SMP in ARC-HS38 cores.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) It provides for cross-core interrupts, multi-core debug
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) hardware semaphores, shared memory,....
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) menuconfig ARC_CACHE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) bool "Enable Cache Support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if ARC_CACHE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) config ARC_CACHE_LINE_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) int "Cache Line Length (as power of 2)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) range 5 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) default "6"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) Starting with ARC700 4.9, Cache line length is configurable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) This option specifies "N", with Line-len = 2 power N
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) Linux only supports same line lengths for I and D caches.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) config ARC_HAS_ICACHE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) bool "Use Instruction Cache"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) config ARC_HAS_DCACHE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) bool "Use Data Cache"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) config ARC_CACHE_PAGES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) bool "Per Page Cache Control"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) This can be used to over-ride the global I/D Cache Enable on a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) per-page basis (but only for pages accessed via MMU such as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) Kernel Virtual address or User Virtual Address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) TLB entries have a per-page Cache Enable Bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) Note that Global I/D ENABLE + Per Page DISABLE works but corollary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) Global DISABLE + Per Page ENABLE won't work
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) config ARC_CACHE_VIPT_ALIASING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) bool "Support VIPT Aliasing D$"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) depends on ARC_HAS_DCACHE && ISA_ARCOMPACT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) endif #ARC_CACHE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) config ARC_HAS_ICCM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) bool "Use ICCM"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) Single Cycle RAMS to store Fast Path Code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) config ARC_ICCM_SZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) int "ICCM Size in KB"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) default "64"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) depends on ARC_HAS_ICCM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) config ARC_HAS_DCCM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) bool "Use DCCM"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) Single Cycle RAMS to store Fast Path Data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) config ARC_DCCM_SZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) int "DCCM Size in KB"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) default "64"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) depends on ARC_HAS_DCCM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) config ARC_DCCM_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) hex "DCCM map address"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) default "0xA0000000"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) depends on ARC_HAS_DCCM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) choice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) prompt "MMU Version"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) default ARC_MMU_V3 if ARC_CPU_770
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) default ARC_MMU_V2 if ARC_CPU_750D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) default ARC_MMU_V4 if ARC_CPU_HS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if ISA_ARCOMPACT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) config ARC_MMU_V1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) bool "MMU v1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) Orig ARC700 MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) config ARC_MMU_V2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) bool "MMU v2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) Fixed the deficiency of v1 - possible thrashing in memcpy scenario
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) when 2 D-TLB and 1 I-TLB entries index into same 2way set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) config ARC_MMU_V3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) bool "MMU v3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) depends on ARC_CPU_770
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) Introduced with ARC700 4.10: New Features
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) Shared Address Spaces (SASID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) config ARC_MMU_V4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) bool "MMU v4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) depends on ISA_ARCV2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) endchoice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) choice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) prompt "MMU Page Size"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) default ARC_PAGE_SIZE_8K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) config ARC_PAGE_SIZE_8K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) bool "8KB"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) Choose between 8k vs 16k
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) config ARC_PAGE_SIZE_16K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) bool "16KB"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) depends on ARC_MMU_V3 || ARC_MMU_V4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) config ARC_PAGE_SIZE_4K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) bool "4KB"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) depends on ARC_MMU_V3 || ARC_MMU_V4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) endchoice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) choice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) prompt "MMU Super Page Size"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) default ARC_HUGEPAGE_2M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) config ARC_HUGEPAGE_2M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) bool "2MB"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) config ARC_HUGEPAGE_16M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) bool "16MB"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) endchoice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) config NODES_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) int "Maximum NUMA Nodes (as a power of 2)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) default "0" if !DISCONTIGMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) default "1" if DISCONTIGMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) depends on NEED_MULTIPLE_NODES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) Accessing memory beyond 1GB (with or w/o PAE) requires 2 memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) zones.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) config ARC_COMPACT_IRQ_LEVELS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) depends on ISA_ARCOMPACT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) bool "Setup Timer IRQ as high Priority"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) depends on !SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) config ARC_FPU_SAVE_RESTORE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) bool "Enable FPU state persistence across context switch"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) ARCompact FPU has internal registers to assist with Double precision
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) Floating Point operations. There are control and stauts registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) for floating point exceptions and rounding modes. These are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) preserved across task context switch when enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) config ARC_CANT_LLSC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) def_bool n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) config ARC_HAS_LLSC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) bool "Insn: LLOCK/SCOND (efficient atomic ops)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) depends on !ARC_CANT_LLSC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) config ARC_HAS_SWAPE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) bool "Insn: SWAPE (endian-swap)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if ISA_ARCV2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) config ARC_USE_UNALIGNED_MEM_ACCESS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) bool "Enable unaligned access in HW"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) select HAVE_EFFICIENT_UNALIGNED_ACCESS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) The ARC HS architecture supports unaligned memory access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) which is disabled by default. Enable unaligned access in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) hardware and use software to use it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) config ARC_HAS_LL64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) bool "Insn: 64bit LDD/STD"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) Enable gcc to generate 64-bit load/store instructions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) ISA mandates even/odd registers to allow encoding of two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) dest operands with 2 possible source operands.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) config ARC_HAS_DIV_REM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) bool "Insn: div, divu, rem, remu"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) config ARC_HAS_ACCL_REGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6 and/or DSP)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) Depending on the configuration, CPU can contain accumulator reg-pair
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) (also referred to as r58:r59). These can also be used by gcc as GPR so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) kernel needs to save/restore per process
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) config ARC_DSP_HANDLED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) def_bool n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) config ARC_DSP_SAVE_RESTORE_REGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) def_bool n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) choice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) prompt "DSP support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) default ARC_DSP_NONE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) Depending on the configuration, CPU can contain DSP registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) (ACC0_GLO, ACC0_GHI, DSP_BFLY0, DSP_CTRL, DSP_FFT_CTRL).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) Bellow is options describing how to handle these registers in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) interrupt entry / exit and in context switch.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) config ARC_DSP_NONE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) bool "No DSP extension presence in HW"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) No DSP extension presence in HW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) config ARC_DSP_KERNEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) bool "DSP extension in HW, no support for userspace"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) select ARC_HAS_ACCL_REGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) select ARC_DSP_HANDLED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) DSP extension presence in HW, no support for DSP-enabled userspace
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) applications. We don't save / restore DSP registers and only do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) some minimal preparations so userspace won't be able to break kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) config ARC_DSP_USERSPACE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) bool "Support DSP for userspace apps"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) select ARC_HAS_ACCL_REGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) select ARC_DSP_HANDLED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) select ARC_DSP_SAVE_RESTORE_REGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) DSP extension presence in HW, support save / restore DSP registers to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) run DSP-enabled userspace applications
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) config ARC_DSP_AGU_USERSPACE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) bool "Support DSP with AGU for userspace apps"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) select ARC_HAS_ACCL_REGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) select ARC_DSP_HANDLED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) select ARC_DSP_SAVE_RESTORE_REGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) DSP and AGU extensions presence in HW, support save / restore DSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) and AGU registers to run DSP-enabled userspace applications
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) endchoice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) config ARC_IRQ_NO_AUTOSAVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) bool "Disable hardware autosave regfile on interrupts"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) default n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) On HS cores, taken interrupt auto saves the regfile on stack.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) This is programmable and can be optionally disabled in which case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) software INTERRUPT_PROLOGUE/EPILGUE do the needed work
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) config ARC_LPB_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) bool "Disable loop buffer (LPB)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) On HS cores, loop buffer (LPB) is programmable in runtime and can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) be optionally disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) endif # ISA_ARCV2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) endmenu # "ARC CPU Configuration"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) config LINUX_LINK_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) hex "Kernel link address"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) default "0x80000000"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) ARC700 divides the 32 bit phy address space into two equal halves
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) Typically Linux kernel is linked at the start of untransalted addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) hence the default value of 0x8zs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) However some customers have peripherals mapped at this addr, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) Linux needs to be scooted a bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) If you don't know what the above means, leave this setting alone.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) This needs to match memory start address specified in Device Tree
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) config LINUX_RAM_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) hex "RAM base address"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) default LINUX_LINK_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) By default Linux is linked at base of RAM. However in some special
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) cases (such as HSDK), Linux can't be linked at start of DDR, hence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) this option.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) config HIGHMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) bool "High Memory Support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) select ARCH_DISCONTIGMEM_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) With ARC 2G:2G address split, only upper 2G is directly addressable by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) kernel. Enable this to potentially allow access to rest of 2G and PAE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) in future
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) config ARC_HAS_PAE40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) bool "Support for the 40-bit Physical Address Extension"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) depends on ISA_ARCV2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) select HIGHMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) select PHYS_ADDR_T_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) Enable access to physical memory beyond 4G, only supported on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) ARC cores with 40 bit Physical Addressing support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) config ARC_KVADDR_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) int "Kernel Virtual Address Space size (MB)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) range 0 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) default "256"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) The kernel address space is carved out of 256MB of translated address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) space for catering to vmalloc, modules, pkmap, fixmap. This however may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) not suffice vmalloc requirements of a 4K CPU EZChip system. So allow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) this to be stretched to 512 MB (by extending into the reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) kernel-user gutter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) config ARC_CURR_IN_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) bool "Dedicate Register r25 for current_task pointer"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) This reserved Register R25 to point to Current Task in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) kernel mode. This saves memory access for each such access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) config ARC_EMUL_UNALIGNED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) bool "Emulate unaligned memory access (userspace only)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) select SYSCTL_ARCH_UNALIGN_NO_WARN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) select SYSCTL_ARCH_UNALIGN_ALLOW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) depends on ISA_ARCOMPACT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) This enables misaligned 16 & 32 bit memory access from user space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) potential bugs in code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) config HZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) int "Timer Frequency"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) default 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) config ARC_METAWARE_HLINK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) bool "Support for Metaware debugger assisted Host access"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) This options allows a Linux userland apps to directly access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) host file system (open/creat/read/write etc) with help from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) Metaware Debugger. This can come in handy for Linux-host communication
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) when there is no real usable peripheral such as EMAC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) menuconfig ARC_DBG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) bool "ARC debugging"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if ARC_DBG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) config ARC_DW2_UNWIND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) bool "Enable DWARF specific kernel stack unwind"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) select KALLSYMS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) Compiles the kernel with DWARF unwind information and can be used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) to get stack backtraces.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) If you say Y here the resulting kernel image will be slightly larger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) but not slower, and it will give very useful debugging information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) If you don't debug the kernel, you can say N, but we may not be able
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) to solve problems without frame unwind information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) config ARC_DBG_TLB_PARANOIA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) bool "Paranoia Checks in Low Level TLB Handlers"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) config ARC_DBG_JUMP_LABEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) bool "Paranoid checks in Static Keys (jump labels) code"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) depends on JUMP_LABEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) default y if STATIC_KEYS_SELFTEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) Enable paranoid checks and self-test of both ARC-specific and generic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) part of static keys (jump labels) related code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) config ARC_BUILTIN_DTB_NAME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) string "Built in DTB"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) Set the name of the DTB to embed in the vmlinux binary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) Leaving it blank selects the minimal "skeleton" dtb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) endmenu # "ARC Architecture Configuration"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) config FORCE_MAX_ZONEORDER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) int "Maximum zone order"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) default "12" if ARC_HUGEPAGE_16M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) default "11"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) source "kernel/power/Kconfig"
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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