Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  linux/arch/alpha/kernel/sys_wildfire.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Wildfire support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *  Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <asm/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <asm/dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <asm/mmu_context.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <asm/core_wildfire.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <asm/hwrpb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <asm/tlbflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include "proto.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include "irq_impl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include "pci_impl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include "machvec_impl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) static unsigned long cached_irq_mask[WILDFIRE_NR_IRQS/(sizeof(long)*8)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) DEFINE_SPINLOCK(wildfire_irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) static int doing_init_irq_hw = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) wildfire_update_irq_hw(unsigned int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	int qbbno = (irq >> 8) & (WILDFIRE_MAX_QBB - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	int pcano = (irq >> 6) & (WILDFIRE_PCA_PER_QBB - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	wildfire_pca *pca;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	volatile unsigned long * enable0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	if (!WILDFIRE_PCA_EXISTS(qbbno, pcano)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		if (!doing_init_irq_hw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 			printk(KERN_ERR "wildfire_update_irq_hw:"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 			       " got irq %d for non-existent PCA %d"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 			       " on QBB %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 			       irq, pcano, qbbno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	pca = WILDFIRE_pca(qbbno, pcano);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	enable0 = (unsigned long *) &pca->pca_int[0].enable; /* ??? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	*enable0 = cached_irq_mask[qbbno * WILDFIRE_PCA_PER_QBB + pcano];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	*enable0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) wildfire_init_irq_hw(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	register wildfire_pca * pca = WILDFIRE_pca(0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	volatile unsigned long * enable0, * enable1, * enable2, *enable3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	volatile unsigned long * target0, * target1, * target2, *target3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	enable0 = (unsigned long *) &pca->pca_int[0].enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	enable1 = (unsigned long *) &pca->pca_int[1].enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	enable2 = (unsigned long *) &pca->pca_int[2].enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	enable3 = (unsigned long *) &pca->pca_int[3].enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	target0 = (unsigned long *) &pca->pca_int[0].target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	target1 = (unsigned long *) &pca->pca_int[1].target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	target2 = (unsigned long *) &pca->pca_int[2].target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	target3 = (unsigned long *) &pca->pca_int[3].target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	*enable0 = *enable1 = *enable2 = *enable3 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	*target0 = (1UL<<8) | WILDFIRE_QBB(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	*target1 = *target2 = *target3 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	*enable0; *enable1; *enable2; *enable3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	*target0; *target1; *target2; *target3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	doing_init_irq_hw = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	/* Need to update only once for every possible PCA. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	for (i = 0; i < WILDFIRE_NR_IRQS; i+=WILDFIRE_IRQ_PER_PCA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		wildfire_update_irq_hw(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	doing_init_irq_hw = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) wildfire_enable_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	unsigned int irq = d->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	if (irq < 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		i8259a_enable_irq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	spin_lock(&wildfire_irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	set_bit(irq, &cached_irq_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	wildfire_update_irq_hw(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	spin_unlock(&wildfire_irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) wildfire_disable_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	unsigned int irq = d->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	if (irq < 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		i8259a_disable_irq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	spin_lock(&wildfire_irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	clear_bit(irq, &cached_irq_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	wildfire_update_irq_hw(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	spin_unlock(&wildfire_irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) wildfire_mask_and_ack_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	unsigned int irq = d->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	if (irq < 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		i8259a_mask_and_ack_irq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	spin_lock(&wildfire_irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	clear_bit(irq, &cached_irq_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	wildfire_update_irq_hw(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	spin_unlock(&wildfire_irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static struct irq_chip wildfire_irq_type = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	.name		= "WILDFIRE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	.irq_unmask	= wildfire_enable_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	.irq_mask	= wildfire_disable_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	.irq_mask_ack	= wildfire_mask_and_ack_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) wildfire_init_irq_per_pca(int qbbno, int pcano)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	int i, irq_bias;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	irq_bias = qbbno * (WILDFIRE_PCA_PER_QBB * WILDFIRE_IRQ_PER_PCA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		 + pcano * WILDFIRE_IRQ_PER_PCA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	unsigned long io_bias;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	/* Only need the following for first PCI bus per PCA. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	io_bias = WILDFIRE_IO(qbbno, pcano<<1) - WILDFIRE_IO_BIAS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	outb(0, DMA1_RESET_REG + io_bias);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	outb(0, DMA2_RESET_REG + io_bias);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	outb(DMA_MODE_CASCADE, DMA2_MODE_REG + io_bias);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	outb(0, DMA2_MASK_REG + io_bias);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	/* ??? Not sure how to do this, yet... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	init_i8259a_irqs(); /* ??? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	for (i = 0; i < 16; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		if (i == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		irq_set_chip_and_handler(i + irq_bias, &wildfire_irq_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 					 handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		irq_set_status_flags(i + irq_bias, IRQ_LEVEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	irq_set_chip_and_handler(36 + irq_bias, &wildfire_irq_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 				 handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	irq_set_status_flags(36 + irq_bias, IRQ_LEVEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	for (i = 40; i < 64; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		irq_set_chip_and_handler(i + irq_bias, &wildfire_irq_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 					 handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		irq_set_status_flags(i + irq_bias, IRQ_LEVEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	if (request_irq(32 + irq_bias, no_action, 0, "isa_enable", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		pr_err("Failed to register isa_enable interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) wildfire_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	int qbbno, pcano;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #if 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	wildfire_init_irq_hw();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	init_i8259a_irqs();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	for (qbbno = 0; qbbno < WILDFIRE_MAX_QBB; qbbno++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	  if (WILDFIRE_QBB_EXISTS(qbbno)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	    for (pcano = 0; pcano < WILDFIRE_PCA_PER_QBB; pcano++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	      if (WILDFIRE_PCA_EXISTS(qbbno, pcano)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		wildfire_init_irq_per_pca(qbbno, pcano);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	      }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	    }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	  }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static void 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) wildfire_device_interrupt(unsigned long vector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	irq = (vector - 0x800) >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	 * bits 10-8:	source QBB ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	 * bits 7-6:	PCA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	 * bits 5-0:	irq in PCA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	handle_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)  * PCI Fixup configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)  * Summary per PCA (2 PCI or HIPPI buses):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)  * Bit      Meaning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)  * 0-15     ISA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)  *32        ISA summary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)  *33        SMI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)  *34        NMI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)  *36        builtin QLogic SCSI (or slot 0 if no IO module)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)  *40        Interrupt Line A from slot 2 PCI0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)  *41        Interrupt Line B from slot 2 PCI0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)  *42        Interrupt Line C from slot 2 PCI0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)  *43        Interrupt Line D from slot 2 PCI0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)  *44        Interrupt Line A from slot 3 PCI0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)  *45        Interrupt Line B from slot 3 PCI0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)  *46        Interrupt Line C from slot 3 PCI0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)  *47        Interrupt Line D from slot 3 PCI0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)  *48        Interrupt Line A from slot 4 PCI1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)  *49        Interrupt Line B from slot 4 PCI1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)  *50        Interrupt Line C from slot 4 PCI1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)  *51        Interrupt Line D from slot 4 PCI1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)  *52        Interrupt Line A from slot 5 PCI1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)  *53        Interrupt Line B from slot 5 PCI1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)  *54        Interrupt Line C from slot 5 PCI1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)  *55        Interrupt Line D from slot 5 PCI1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)  *56        Interrupt Line A from slot 6 PCI1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)  *57        Interrupt Line B from slot 6 PCI1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)  *58        Interrupt Line C from slot 6 PCI1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)  *50        Interrupt Line D from slot 6 PCI1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)  *60        Interrupt Line A from slot 7 PCI1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)  *61        Interrupt Line B from slot 7 PCI1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)  *62        Interrupt Line C from slot 7 PCI1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)  *63        Interrupt Line D from slot 7 PCI1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)  * 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)  * IdSel	
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)  *   0	 Cypress Bridge I/O (ISA summary interrupt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)  *   1	 64 bit PCI 0 option slot 1 (SCSI QLogic builtin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)  *   2	 64 bit PCI 0 option slot 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)  *   3	 64 bit PCI 0 option slot 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)  *   4	 64 bit PCI 1 option slot 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)  *   5	 64 bit PCI 1 option slot 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)  *   6	 64 bit PCI 1 option slot 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)  *   7	 64 bit PCI 1 option slot 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) wildfire_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	static char irq_tab[8][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		/*INT    INTA   INTB   INTC   INTD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		{ -1,    -1,    -1,    -1,    -1}, /* IdSel 0 ISA Bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		{ 36,    36,    36+1, 36+2, 36+3}, /* IdSel 1 SCSI builtin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		{ 40,    40,    40+1, 40+2, 40+3}, /* IdSel 2 PCI 0 slot 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		{ 44,    44,    44+1, 44+2, 44+3}, /* IdSel 3 PCI 0 slot 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		{ 48,    48,    48+1, 48+2, 48+3}, /* IdSel 4 PCI 1 slot 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		{ 52,    52,    52+1, 52+2, 52+3}, /* IdSel 5 PCI 1 slot 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		{ 56,    56,    56+1, 56+2, 56+3}, /* IdSel 6 PCI 1 slot 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		{ 60,    60,    60+1, 60+2, 60+3}, /* IdSel 7 PCI 1 slot 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	long min_idsel = 0, max_idsel = 7, irqs_per_slot = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	struct pci_controller *hose = dev->sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	int irq = COMMON_TABLE_LOOKUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	if (irq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		int qbbno = hose->index >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		int pcano = (hose->index >> 1) & 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		irq += (qbbno << 8) + (pcano << 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)  * The System Vectors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct alpha_machine_vector wildfire_mv __initmv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	.vector_name		= "WILDFIRE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	DO_EV6_MMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	DO_DEFAULT_RTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	DO_WILDFIRE_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	.machine_check		= wildfire_machine_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	.max_isa_dma_address	= ALPHA_MAX_ISA_DMA_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	.min_io_address		= DEFAULT_IO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	.min_mem_address	= DEFAULT_MEM_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	.nr_irqs		= WILDFIRE_NR_IRQS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	.device_interrupt	= wildfire_device_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	.init_arch		= wildfire_init_arch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	.init_irq		= wildfire_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	.init_rtc		= common_init_rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	.init_pci		= common_init_pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	.kill_arch		= wildfire_kill_arch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	.pci_map_irq		= wildfire_map_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	.pci_swizzle		= common_swizzle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	.pa_to_nid		= wildfire_pa_to_nid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	.cpuid_to_nid		= wildfire_cpuid_to_nid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	.node_mem_start		= wildfire_node_mem_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	.node_mem_size		= wildfire_node_mem_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) ALIAS_MV(wildfire)