^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/alpha/kernel/sys_titan.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1995 David A Rusling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 1996, 1999 Jay A Estabrook
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 1998, 1999 Richard Henderson
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 1999, 2000 Jeff Wiedemeier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Code supporting TITAN systems (EV6+TITAN), currently:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Privateer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Falcon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Granite
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/mmu_context.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/core_titan.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <asm/hwrpb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <asm/tlbflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include "proto.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include "irq_impl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include "pci_impl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include "machvec_impl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include "err_impl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * Titan generic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * Titan supports up to 4 CPUs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static unsigned long titan_cpu_irq_affinity[4] = { ~0UL, ~0UL, ~0UL, ~0UL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * Mask is set (1) if enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static unsigned long titan_cached_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * Need SMP-safe access to interrupt CSRs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) DEFINE_SPINLOCK(titan_irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) titan_update_irq_hw(unsigned long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) register titan_cchip *cchip = TITAN_cchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) unsigned long isa_enable = 1UL << 55;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) register int bcpu = boot_cpuid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) cpumask_t cpm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) volatile unsigned long *dim0, *dim1, *dim2, *dim3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) unsigned long mask0, mask1, mask2, mask3, dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) cpumask_copy(&cpm, cpu_present_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) mask &= ~isa_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) mask0 = mask & titan_cpu_irq_affinity[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) mask1 = mask & titan_cpu_irq_affinity[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) mask2 = mask & titan_cpu_irq_affinity[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) mask3 = mask & titan_cpu_irq_affinity[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (bcpu == 0) mask0 |= isa_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) else if (bcpu == 1) mask1 |= isa_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) else if (bcpu == 2) mask2 |= isa_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) else mask3 |= isa_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) dim0 = &cchip->dim0.csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) dim1 = &cchip->dim1.csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) dim2 = &cchip->dim2.csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) dim3 = &cchip->dim3.csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (!cpumask_test_cpu(0, &cpm)) dim0 = &dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (!cpumask_test_cpu(1, &cpm)) dim1 = &dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (!cpumask_test_cpu(2, &cpm)) dim2 = &dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (!cpumask_test_cpu(3, &cpm)) dim3 = &dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) *dim0 = mask0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) *dim1 = mask1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) *dim2 = mask2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) *dim3 = mask3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) *dim0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) *dim1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) *dim2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) *dim3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) volatile unsigned long *dimB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) dimB = &cchip->dim0.csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (bcpu == 1) dimB = &cchip->dim1.csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) else if (bcpu == 2) dimB = &cchip->dim2.csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) else if (bcpu == 3) dimB = &cchip->dim3.csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) *dimB = mask | isa_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) *dimB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) titan_enable_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned int irq = d->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) spin_lock(&titan_irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) titan_cached_irq_mask |= 1UL << (irq - 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) titan_update_irq_hw(titan_cached_irq_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) spin_unlock(&titan_irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) titan_disable_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) unsigned int irq = d->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) spin_lock(&titan_irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) titan_cached_irq_mask &= ~(1UL << (irq - 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) titan_update_irq_hw(titan_cached_irq_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) spin_unlock(&titan_irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) titan_cpu_set_irq_affinity(unsigned int irq, cpumask_t affinity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) for (cpu = 0; cpu < 4; cpu++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (cpumask_test_cpu(cpu, &affinity))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) titan_cpu_irq_affinity[cpu] |= 1UL << irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) titan_cpu_irq_affinity[cpu] &= ~(1UL << irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) titan_set_irq_affinity(struct irq_data *d, const struct cpumask *affinity,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) bool force)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) unsigned int irq = d->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) spin_lock(&titan_irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) titan_cpu_set_irq_affinity(irq - 16, *affinity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) titan_update_irq_hw(titan_cached_irq_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) spin_unlock(&titan_irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) titan_device_interrupt(unsigned long vector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) printk("titan_device_interrupt: NOT IMPLEMENTED YET!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) titan_srm_device_interrupt(unsigned long vector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) irq = (vector - 0x800) >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) handle_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) init_titan_irqs(struct irq_chip * ops, int imin, int imax)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) long i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) for (i = imin; i <= imax; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) irq_set_chip_and_handler(i, ops, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) irq_set_status_flags(i, IRQ_LEVEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static struct irq_chip titan_irq_type = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .name = "TITAN",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .irq_unmask = titan_enable_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .irq_mask = titan_disable_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .irq_mask_ack = titan_disable_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .irq_set_affinity = titan_set_irq_affinity,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static irqreturn_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) titan_intr_nop(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * This is a NOP interrupt handler for the purposes of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * event counting -- just return.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) titan_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (alpha_using_srm && !alpha_mv.device_interrupt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) alpha_mv.device_interrupt = titan_srm_device_interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (!alpha_mv.device_interrupt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) alpha_mv.device_interrupt = titan_device_interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) titan_update_irq_hw(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) init_titan_irqs(&titan_irq_type, 16, 63 + 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) titan_legacy_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* init the legacy dma controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) outb(0, DMA1_RESET_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) outb(0, DMA2_RESET_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) outb(DMA_MODE_CASCADE, DMA2_MODE_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) outb(0, DMA2_MASK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* init the legacy irq controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) init_i8259a_irqs();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* init the titan irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) titan_init_irq();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) titan_dispatch_irqs(u64 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) unsigned long vector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * Mask down to those interrupts which are enable on this processor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) mask &= titan_cpu_irq_affinity[smp_processor_id()];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * Dispatch all requested interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) while (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* convert to SRM vector... priority is <63> -> <0> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) vector = 63 - __kernel_ctlz(mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) mask &= ~(1UL << vector); /* clear it out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) vector = 0x900 + (vector << 4); /* convert to SRM vector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* dispatch it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) alpha_mv.device_interrupt(vector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * Titan Family
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) titan_request_irq(unsigned int irq, irq_handler_t handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) unsigned long irqflags, const char *devname,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) err = request_irq(irq, handler, irqflags, devname, dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) printk("titan_request_irq for IRQ %d returned %d; ignoring\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) irq, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) titan_late_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * Enable the system error interrupts. These interrupts are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * all reported to the kernel as machine checks, so the handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * is a nop so it can be called to count the individual events.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) titan_request_irq(63+16, titan_intr_nop, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) "CChip Error", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) titan_request_irq(62+16, titan_intr_nop, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) "PChip 0 H_Error", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) titan_request_irq(61+16, titan_intr_nop, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) "PChip 1 H_Error", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) titan_request_irq(60+16, titan_intr_nop, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) "PChip 0 C_Error", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) titan_request_irq(59+16, titan_intr_nop, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) "PChip 1 C_Error", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * Register our error handlers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) titan_register_error_handlers();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * Check if the console left us any error logs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) cdl_check_console_data_log();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) titan_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) u8 intline;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* Get the current intline. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &intline);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) irq = intline;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* Is it explicitly routed through ISA? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if ((irq & 0xF0) == 0xE0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* Offset by 16 to make room for ISA interrupts 0 - 15. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return irq + 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) titan_init_pci(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * This isn't really the right place, but there's some init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * that needs to be done after everything is basically up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) titan_late_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* Indicate that we trust the console to configure things properly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) pci_set_flags(PCI_PROBE_ONLY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) common_init_pci();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) SMC669_Init(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) locate_and_init_vga(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * Privateer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) privateer_init_pci(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * Hook a couple of extra err interrupts that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * common titan code won't.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) titan_request_irq(53+16, titan_intr_nop, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) "NMI", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) titan_request_irq(50+16, titan_intr_nop, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) "Temperature Warning", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * Finish with the common version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return titan_init_pci();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * The System Vectors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) struct alpha_machine_vector titan_mv __initmv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .vector_name = "TITAN",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) DO_EV6_MMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) DO_DEFAULT_RTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) DO_TITAN_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .machine_check = titan_machine_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .min_io_address = DEFAULT_IO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .min_mem_address = DEFAULT_MEM_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .pci_dac_offset = TITAN_DAC_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .nr_irqs = 80, /* 64 + 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* device_interrupt will be filled in by titan_init_irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .agp_info = titan_agp_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .init_arch = titan_init_arch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .init_irq = titan_legacy_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .init_rtc = common_init_rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .init_pci = titan_init_pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .kill_arch = titan_kill_arch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .pci_map_irq = titan_map_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .pci_swizzle = common_swizzle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) ALIAS_MV(titan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct alpha_machine_vector privateer_mv __initmv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .vector_name = "PRIVATEER",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) DO_EV6_MMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) DO_DEFAULT_RTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) DO_TITAN_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .machine_check = privateer_machine_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .min_io_address = DEFAULT_IO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .min_mem_address = DEFAULT_MEM_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .pci_dac_offset = TITAN_DAC_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .nr_irqs = 80, /* 64 + 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* device_interrupt will be filled in by titan_init_irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .agp_info = titan_agp_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .init_arch = titan_init_arch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .init_irq = titan_legacy_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .init_rtc = common_init_rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .init_pci = privateer_init_pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .kill_arch = titan_kill_arch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .pci_map_irq = titan_map_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .pci_swizzle = common_swizzle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* No alpha_mv alias for privateer since we compile it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) in unconditionally with titan; setup_arch knows how to cope. */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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