^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/alpha/kernel/sys_takara.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1995 David A Rusling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 1996 Jay A Estabrook
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 1998, 1999 Richard Henderson
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Code supporting the TAKARA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/mmu_context.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/core_cia.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/tlbflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "proto.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "irq_impl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "pci_impl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "machvec_impl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "pc873xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* Note mask bit is true for DISABLED irqs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static unsigned long cached_irq_mask[2] = { -1, -1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) takara_update_irq_hw(unsigned long irq, unsigned long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) int regaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) mask = (irq >= 64 ? mask << 16 : mask >> ((irq - 16) & 0x30));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) regaddr = 0x510 + (((irq - 16) >> 2) & 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) outl(mask & 0xffff0000UL, regaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) takara_enable_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) unsigned int irq = d->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) unsigned long mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) mask = (cached_irq_mask[irq >= 64] &= ~(1UL << (irq & 63)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) takara_update_irq_hw(irq, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) takara_disable_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) unsigned int irq = d->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) unsigned long mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) mask = (cached_irq_mask[irq >= 64] |= 1UL << (irq & 63));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) takara_update_irq_hw(irq, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static struct irq_chip takara_irq_type = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .name = "TAKARA",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .irq_unmask = takara_enable_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .irq_mask = takara_disable_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .irq_mask_ack = takara_disable_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) takara_device_interrupt(unsigned long vector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) unsigned intstatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * The PALcode will have passed us vectors 0x800 or 0x810,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * which are fairly arbitrary values and serve only to tell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * us whether an interrupt has come in on IRQ0 or IRQ1. If
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * it's IRQ1 it's a PCI interrupt; if it's IRQ0, it's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * probably ISA, but PCI interrupts can come through IRQ0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * as well if the interrupt controller isn't in accelerated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * OTOH, the accelerator thing doesn't seem to be working
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * overly well, so what we'll do instead is try directly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * examining the Master Interrupt Register to see if it's a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * PCI interrupt, and if _not_ then we'll pass it on to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * ISA handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) intstatus = inw(0x500) & 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (intstatus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * This is a PCI interrupt. Check each bit and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * despatch an interrupt if it's set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (intstatus & 8) handle_irq(16+3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (intstatus & 4) handle_irq(16+2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (intstatus & 2) handle_irq(16+1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (intstatus & 1) handle_irq(16+0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) isa_device_interrupt (vector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) takara_srm_device_interrupt(unsigned long vector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) int irq = (vector - 0x800) >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) handle_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) takara_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) long i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) init_i8259a_irqs();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (alpha_using_srm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) alpha_mv.device_interrupt = takara_srm_device_interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) unsigned int ctlreg = inl(0x500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* Return to non-accelerated mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) ctlreg &= ~0x8000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) outl(ctlreg, 0x500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* Enable the PCI interrupt register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) ctlreg = 0x05107c00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) outl(ctlreg, 0x500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) for (i = 16; i < 128; i += 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) takara_update_irq_hw(i, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) for (i = 16; i < 128; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) irq_set_chip_and_handler(i, &takara_irq_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) irq_set_status_flags(i, IRQ_LEVEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) common_init_isa_dma();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * The Takara has PCI devices 1, 2, and 3 configured to slots 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * 19, and 18 respectively, in the default configuration. They can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * also be jumpered to slots 8, 7, and 6 respectively, which is fun
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * because the SIO ISA bridge can also be slot 7. However, the SIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * doesn't explicitly generate PCI-type interrupts, so we can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * assign it whatever the hell IRQ we like and it doesn't matter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) takara_map_irq_srm(const struct pci_dev *dev, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static char irq_tab[15][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) { 16+3, 16+3, 16+3, 16+3, 16+3}, /* slot 6 == device 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) { 16+2, 16+2, 16+2, 16+2, 16+2}, /* slot 7 == device 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) { 16+1, 16+1, 16+1, 16+1, 16+1}, /* slot 8 == device 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) { -1, -1, -1, -1, -1}, /* slot 9 == nothing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) { -1, -1, -1, -1, -1}, /* slot 10 == nothing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) { -1, -1, -1, -1, -1}, /* slot 11 == nothing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* These are behind the bridges. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) { 12, 12, 13, 14, 15}, /* slot 12 == nothing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) { 8, 8, 9, 19, 11}, /* slot 13 == nothing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) { 4, 4, 5, 6, 7}, /* slot 14 == nothing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) { 0, 0, 1, 2, 3}, /* slot 15 == nothing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) { -1, -1, -1, -1, -1}, /* slot 16 == nothing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {64+ 0, 64+0, 64+1, 64+2, 64+3}, /* slot 17= device 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {48+ 0, 48+0, 48+1, 48+2, 48+3}, /* slot 18= device 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {32+ 0, 32+0, 32+1, 32+2, 32+3}, /* slot 19= device 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {16+ 0, 16+0, 16+1, 16+2, 16+3}, /* slot 20= device 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) const long min_idsel = 6, max_idsel = 20, irqs_per_slot = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) int irq = COMMON_TABLE_LOOKUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (irq >= 0 && irq < 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* Guess that we are behind a bridge. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) unsigned int busslot = PCI_SLOT(dev->bus->self->devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) irq += irq_tab[busslot-min_idsel][0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) takara_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static char irq_tab[15][5] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) { 16+3, 16+3, 16+3, 16+3, 16+3}, /* slot 6 == device 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) { 16+2, 16+2, 16+2, 16+2, 16+2}, /* slot 7 == device 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) { 16+1, 16+1, 16+1, 16+1, 16+1}, /* slot 8 == device 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) { -1, -1, -1, -1, -1}, /* slot 9 == nothing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) { -1, -1, -1, -1, -1}, /* slot 10 == nothing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) { -1, -1, -1, -1, -1}, /* slot 11 == nothing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) { -1, -1, -1, -1, -1}, /* slot 12 == nothing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) { -1, -1, -1, -1, -1}, /* slot 13 == nothing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) { -1, -1, -1, -1, -1}, /* slot 14 == nothing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) { -1, -1, -1, -1, -1}, /* slot 15 == nothing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) { -1, -1, -1, -1, -1}, /* slot 16 == nothing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) { -1, -1, -1, -1, -1}, /* slot 17 == nothing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) { 16+3, 16+3, 16+3, 16+3, 16+3}, /* slot 18 == device 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) { 16+2, 16+2, 16+2, 16+2, 16+2}, /* slot 19 == device 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) { 16+1, 16+1, 16+1, 16+1, 16+1}, /* slot 20 == device 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) const long min_idsel = 6, max_idsel = 20, irqs_per_slot = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return COMMON_TABLE_LOOKUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static u8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) takara_swizzle(struct pci_dev *dev, u8 *pinp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) int slot = PCI_SLOT(dev->devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) int pin = *pinp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) unsigned int ctlreg = inl(0x500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) unsigned int busslot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (!dev->bus->self)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) busslot = PCI_SLOT(dev->bus->self->devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* Check for built-in bridges. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (dev->bus->number != 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) && busslot > 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) && ((1<<(36-busslot)) & ctlreg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (pin == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) pin += (20 - busslot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) printk(KERN_WARNING "takara_swizzle: can only "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) "handle cards with INTA IRQ pin.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* Must be a card-based bridge. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) printk(KERN_WARNING "takara_swizzle: cannot handle "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) "card-bridge behind builtin bridge yet.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) *pinp = pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) takara_init_pci(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (alpha_using_srm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) alpha_mv.pci_map_irq = takara_map_irq_srm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) cia_init_pci();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (pc873xx_probe() == -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) printk(KERN_ERR "Probing for PC873xx Super IO chip failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) printk(KERN_INFO "Found %s Super IO chip at 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) pc873xx_get_model(), pc873xx_get_base());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) pc873xx_enable_ide();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * The System Vector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct alpha_machine_vector takara_mv __initmv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .vector_name = "Takara",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) DO_EV5_MMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) DO_DEFAULT_RTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) DO_CIA_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .machine_check = cia_machine_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .min_io_address = DEFAULT_IO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .min_mem_address = CIA_DEFAULT_MEM_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .nr_irqs = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .device_interrupt = takara_device_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .init_arch = cia_init_arch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .init_irq = takara_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .init_rtc = common_init_rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .init_pci = takara_init_pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .kill_arch = cia_kill_arch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .pci_map_irq = takara_map_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .pci_swizzle = takara_swizzle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) ALIAS_MV(takara)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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