^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/alpha/kernel/sys_sx164.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1995 David A Rusling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 1996 Jay A Estabrook
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 1998, 1999, 2000 Richard Henderson
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Code supporting the SX164 (PCA56+PYXIS).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/mmu_context.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/core_cia.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/hwrpb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/tlbflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/special_insns.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "proto.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "irq_impl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include "pci_impl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include "machvec_impl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) sx164_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) outb(0, DMA1_RESET_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) outb(0, DMA2_RESET_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) outb(DMA_MODE_CASCADE, DMA2_MODE_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) outb(0, DMA2_MASK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) if (alpha_using_srm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) alpha_mv.device_interrupt = srm_device_interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) init_i8259a_irqs();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* Not interested in the bogus interrupts (0,3,4,5,40-47),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) NMI (1), or HALT (2). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) if (alpha_using_srm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) init_srm_irqs(40, 0x3f0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) init_pyxis_irqs(0xff00003f0000UL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) if (request_irq(16 + 6, no_action, 0, "timer-cascade", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) pr_err("Failed to register timer-cascade interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * PCI Fixup configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * Summary @ PYXIS_INT_REQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * Bit Meaning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * 0 RSVD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * 1 NMI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * 2 Halt/Reset switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * 3 MBZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * 4 RAZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * 5 RAZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * 6 Interval timer (RTC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * 7 PCI-ISA Bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * 8 Interrupt Line A from slot 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * 9 Interrupt Line A from slot 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) *10 Interrupt Line A from slot 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) *11 Interrupt Line A from slot 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) *12 Interrupt Line B from slot 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) *13 Interrupt Line B from slot 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) *14 Interrupt Line B from slot 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) *15 Interrupt line B from slot 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) *16 Interrupt Line C from slot 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) *17 Interrupt Line C from slot 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) *18 Interrupt Line C from slot 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) *19 Interrupt Line C from slot 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) *20 Interrupt Line D from slot 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) *21 Interrupt Line D from slot 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) *22 Interrupt Line D from slot 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) *23 Interrupt Line D from slot 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * IdSel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * 5 32 bit PCI option slot 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * 6 64 bit PCI option slot 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * 7 64 bit PCI option slot 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * 8 Cypress I/O
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * 9 32 bit PCI option slot 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) sx164_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static char irq_tab[5][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /*INT INTA INTB INTC INTD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) { 16+ 9, 16+ 9, 16+13, 16+17, 16+21}, /* IdSel 5 slot 2 J17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) { 16+11, 16+11, 16+15, 16+19, 16+23}, /* IdSel 6 slot 0 J19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { 16+10, 16+10, 16+14, 16+18, 16+22}, /* IdSel 7 slot 1 J18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) { -1, -1, -1, -1, -1}, /* IdSel 8 SIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) { 16+ 8, 16+ 8, 16+12, 16+16, 16+20} /* IdSel 9 slot 3 J15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) const long min_idsel = 5, max_idsel = 9, irqs_per_slot = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return COMMON_TABLE_LOOKUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) sx164_init_pci(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) cia_init_pci();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) SMC669_Init(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) sx164_init_arch(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * OSF palcode v1.23 forgets to enable PCA56 Motion Video
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * Instructions. Let's enable it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * We have to check palcode revision because CSERVE interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * is subject to change without notice. For example, it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * has been changed completely since v1.16 (found in MILO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * distribution). -ink
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct percpu_struct *cpu = (struct percpu_struct*)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) ((char*)hwrpb + hwrpb->processor_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (amask(AMASK_MAX) != 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) && alpha_using_srm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) && (cpu->pal_revision & 0xffff) <= 0x117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) __asm__ __volatile__(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) "lda $16,8($31)\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) "call_pal 9\n" /* Allow PALRES insns in kernel mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ".long 0x64000118\n\n" /* hw_mfpr $0,icsr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) "ldah $16,(1<<(19-16))($31)\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) "or $0,$16,$0\n" /* set MVE bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) ".long 0x74000118\n" /* hw_mtpr $0,icsr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) "lda $16,9($31)\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) "call_pal 9" /* Disable PALRES insns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) : : : "$0", "$16");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) printk("PCA56 MVI set enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) pyxis_init_arch();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * The System Vector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct alpha_machine_vector sx164_mv __initmv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .vector_name = "SX164",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) DO_EV5_MMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) DO_DEFAULT_RTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) DO_PYXIS_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .machine_check = cia_machine_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .min_io_address = DEFAULT_IO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .min_mem_address = DEFAULT_MEM_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .pci_dac_offset = PYXIS_DAC_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .nr_irqs = 48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .device_interrupt = pyxis_device_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .init_arch = sx164_init_arch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .init_irq = sx164_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .init_rtc = common_init_rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .init_pci = sx164_init_pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .kill_arch = cia_kill_arch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .pci_map_irq = sx164_map_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .pci_swizzle = common_swizzle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) ALIAS_MV(sx164)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags