^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/alpha/kernel/sys_sio.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1995 David A Rusling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 1996 Jay A Estabrook
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 1998, 1999 Richard Henderson
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Code for all boards that route the PCI interrupts through the SIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * PCI/ISA bridge. This includes Noname (AXPpci33), Multia (UDB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Kenetics's Platform 2000, Avanti (AlphaStation), XL, and AlphaBook1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/screen_info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/compiler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/mmu_context.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/core_apecs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/core_lca.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <asm/tlbflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include "proto.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include "irq_impl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include "pci_impl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include "machvec_impl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include "pc873xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #if defined(ALPHA_RESTORE_SRM_SETUP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* Save LCA configuration data as the console had it set up. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) unsigned int orig_route_tab; /* for SAVE/RESTORE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) } saved_config __attribute((common));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) sio_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) if (alpha_using_srm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) alpha_mv.device_interrupt = srm_device_interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) init_i8259a_irqs();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) common_init_isa_dma();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static inline void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) alphabook1_init_arch(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* The AlphaBook1 has LCD video fixed at 800x600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 37 rows and 100 cols. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) screen_info.orig_y = 37;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) screen_info.orig_video_cols = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) screen_info.orig_video_lines = 37;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) lca_init_arch();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * sio_route_tab selects irq routing in PCI/ISA bridge so that:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * PIRQ0 -> irq 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * PIRQ1 -> irq 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * PIRQ2 -> irq 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * PIRQ3 -> irq 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * This probably ought to be configurable via MILO. For
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * example, sound boards seem to like using IRQ 9.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * This is NOT how we should do it. PIRQ0-X should have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * their own IRQs, the way intel uses the IO-APIC IRQs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) sio_pci_route(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) unsigned int orig_route_tab;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* First, ALWAYS read and print the original setting. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) pci_bus_read_config_dword(pci_isa_hose->bus, PCI_DEVFN(7, 0), 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) &orig_route_tab);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) printk("%s: PIRQ original 0x%x new 0x%x\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) orig_route_tab, alpha_mv.sys.sio.route_tab);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #if defined(ALPHA_RESTORE_SRM_SETUP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) saved_config.orig_route_tab = orig_route_tab;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* Now override with desired setting. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) pci_bus_write_config_dword(pci_isa_hose->bus, PCI_DEVFN(7, 0), 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) alpha_mv.sys.sio.route_tab);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static bool sio_pci_dev_irq_needs_level(const struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if ((dev->class >> 16 == PCI_BASE_CLASS_BRIDGE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) (dev->class >> 8 != PCI_CLASS_BRIDGE_PCMCIA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static unsigned int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) sio_collect_irq_levels(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) unsigned int level_bits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct pci_dev *dev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* Iterate through the devices, collecting IRQ levels. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) for_each_pci_dev(dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (!sio_pci_dev_irq_needs_level(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (dev->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) level_bits |= (1 << dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return level_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static void __sio_fixup_irq_levels(unsigned int level_bits, bool reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) unsigned int old_level_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * Now, make all PCI interrupts level sensitive. Notice:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * these registers must be accessed byte-wise. inw()/outw()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * don't work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * Make sure to turn off any level bits set for IRQs 9,10,11,15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * so that the only bits getting set are for devices actually found.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * Note that we do preserve the remainder of the bits, which we hope
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * will be set correctly by ARC/SRM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * Note: we at least preserve any level-set bits on AlphaBook1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) old_level_bits = inb(0x4d0) | (inb(0x4d1) << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) old_level_bits &= 0x71ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) level_bits |= old_level_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) outb((level_bits >> 0) & 0xff, 0x4d0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) outb((level_bits >> 8) & 0xff, 0x4d1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) sio_fixup_irq_levels(unsigned int level_bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) __sio_fixup_irq_levels(level_bits, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) noname_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * The Noname board has 5 PCI slots with each of the 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * interrupt pins routed to different pins on the PCI/ISA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * bridge (PIRQ0-PIRQ3). The table below is based on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * information available at:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * http://ftp.digital.com/pub/DEC/axppci/ref_interrupts.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * I have no information on the Avanti interrupt routing, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * the routing seems to be identical to the Noname except
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * that the Avanti has an additional slot whose routing I'm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * unsure of.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * pirq_tab[0] is a fake entry to deal with old PCI boards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * that have the interrupt pin number hardwired to 0 (meaning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * that they use the default INTA line, if they are interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * driven at all).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static char irq_tab[][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /*INT A B C D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) { 3, 3, 3, 3, 3}, /* idsel 6 (53c810) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {-1, -1, -1, -1, -1}, /* idsel 7 (SIO: PCI/ISA bridge) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) { 2, 2, -1, -1, -1}, /* idsel 8 (Hack: slot closest ISA) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {-1, -1, -1, -1, -1}, /* idsel 9 (unused) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {-1, -1, -1, -1, -1}, /* idsel 10 (unused) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) { 0, 0, 2, 1, 0}, /* idsel 11 KN25_PCI_SLOT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) { 1, 1, 0, 2, 1}, /* idsel 12 KN25_PCI_SLOT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) { 2, 2, 1, 0, 2}, /* idsel 13 KN25_PCI_SLOT2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) { 0, 0, 0, 0, 0}, /* idsel 14 AS255 TULIP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) const long min_idsel = 6, max_idsel = 14, irqs_per_slot = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) int irq = COMMON_TABLE_LOOKUP, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) tmp = __kernel_extbl(alpha_mv.sys.sio.route_tab, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) irq = irq >= 0 ? tmp : -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* Fixup IRQ level if an actual IRQ mapping is detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (sio_pci_dev_irq_needs_level(dev) && irq >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) __sio_fixup_irq_levels(1 << irq, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) p2k_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static char irq_tab[][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /*INT A B C D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) { 0, 0, -1, -1, -1}, /* idsel 6 (53c810) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {-1, -1, -1, -1, -1}, /* idsel 7 (SIO: PCI/ISA bridge) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) { 1, 1, 2, 3, 0}, /* idsel 8 (slot A) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) { 2, 2, 3, 0, 1}, /* idsel 9 (slot B) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {-1, -1, -1, -1, -1}, /* idsel 10 (unused) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {-1, -1, -1, -1, -1}, /* idsel 11 (unused) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) { 3, 3, -1, -1, -1}, /* idsel 12 (CMD0646) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) const long min_idsel = 6, max_idsel = 12, irqs_per_slot = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) int irq = COMMON_TABLE_LOOKUP, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) tmp = __kernel_extbl(alpha_mv.sys.sio.route_tab, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return irq >= 0 ? tmp : -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static inline void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) noname_init_pci(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) common_init_pci();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) sio_pci_route();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) sio_fixup_irq_levels(sio_collect_irq_levels());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (pc873xx_probe() == -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) printk(KERN_ERR "Probing for PC873xx Super IO chip failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) printk(KERN_INFO "Found %s Super IO chip at 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) pc873xx_get_model(), pc873xx_get_base());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* Enabling things in the Super IO chip doesn't actually
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * configure and enable things, the legacy drivers still
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * need to do the actual configuration and enabling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * This only unblocks them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #if !defined(CONFIG_ALPHA_AVANTI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* Don't bother on the Avanti family.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * None of them had on-board IDE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) pc873xx_enable_ide();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) pc873xx_enable_epp19();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static inline void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) alphabook1_init_pci(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) unsigned char orig, config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) common_init_pci();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) sio_pci_route();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * On the AlphaBook1, the PCMCIA chip (Cirrus 6729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * is sensitive to PCI bus bursts, so we must DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * burst mode for the NCR 8xx SCSI... :-(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * Note that the NCR810 SCSI driver must preserve the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * setting of the bit in order for this to work. At the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * moment (2.0.29), ncr53c8xx.c does NOT do this, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * 53c7,8xx.c DOES.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) dev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) while ((dev = pci_get_device(PCI_VENDOR_ID_NCR, PCI_ANY_ID, dev))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (dev->device == PCI_DEVICE_ID_NCR_53C810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) || dev->device == PCI_DEVICE_ID_NCR_53C815
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) || dev->device == PCI_DEVICE_ID_NCR_53C820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) || dev->device == PCI_DEVICE_ID_NCR_53C825) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) unsigned long io_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) unsigned char ctest4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) io_port = dev->resource[0].start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) ctest4 = inb(io_port+0x21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (!(ctest4 & 0x80)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) printk("AlphaBook1 NCR init: setting"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) " burst disable\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) outb(ctest4 | 0x80, io_port+0x21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* Do not set *ANY* level triggers for AlphaBook1. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) sio_fixup_irq_levels(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* Make sure that register PR1 indicates 1Mb mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) outb(0x0f, 0x3ce); orig = inb(0x3cf); /* read PR5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) outb(0x0f, 0x3ce); outb(0x05, 0x3cf); /* unlock PR0-4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) outb(0x0b, 0x3ce); config = inb(0x3cf); /* read PR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if ((config & 0xc0) != 0xc0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) printk("AlphaBook1 VGA init: setting 1Mb memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) config |= 0xc0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) outb(0x0b, 0x3ce); outb(config, 0x3cf); /* write PR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) outb(0x0f, 0x3ce); outb(orig, 0x3cf); /* (re)lock PR0-4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) sio_kill_arch(int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #if defined(ALPHA_RESTORE_SRM_SETUP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* Since we cannot read the PCI DMA Window CSRs, we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * cannot restore them here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * However, we CAN read the PIRQ route register, so restore it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * now...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) pci_bus_write_config_dword(pci_isa_hose->bus, PCI_DEVFN(7, 0), 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) saved_config.orig_route_tab);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * The System Vectors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_BOOK1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct alpha_machine_vector alphabook1_mv __initmv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .vector_name = "AlphaBook1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) DO_EV4_MMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) DO_DEFAULT_RTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) DO_LCA_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .machine_check = lca_machine_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .min_io_address = DEFAULT_IO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .nr_irqs = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .device_interrupt = isa_device_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .init_arch = alphabook1_init_arch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .init_irq = sio_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .init_rtc = common_init_rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .init_pci = alphabook1_init_pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .kill_arch = sio_kill_arch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .pci_map_irq = noname_map_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .pci_swizzle = common_swizzle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .sys = { .sio = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* NCR810 SCSI is 14, PCMCIA controller is 15. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .route_tab = 0x0e0f0a0a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) ALIAS_MV(alphabook1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_AVANTI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct alpha_machine_vector avanti_mv __initmv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .vector_name = "Avanti",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) DO_EV4_MMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) DO_DEFAULT_RTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) DO_APECS_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .machine_check = apecs_machine_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .min_io_address = DEFAULT_IO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .nr_irqs = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .device_interrupt = isa_device_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .init_arch = apecs_init_arch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .init_irq = sio_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .init_rtc = common_init_rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .init_pci = noname_init_pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .kill_arch = sio_kill_arch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .pci_map_irq = noname_map_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .pci_swizzle = common_swizzle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .sys = { .sio = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .route_tab = 0x0b0a050f, /* leave 14 for IDE, 9 for SND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) ALIAS_MV(avanti)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_NONAME)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct alpha_machine_vector noname_mv __initmv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .vector_name = "Noname",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) DO_EV4_MMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) DO_DEFAULT_RTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) DO_LCA_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .machine_check = lca_machine_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .min_io_address = DEFAULT_IO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .nr_irqs = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .device_interrupt = srm_device_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .init_arch = lca_init_arch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .init_irq = sio_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .init_rtc = common_init_rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .init_pci = noname_init_pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .kill_arch = sio_kill_arch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .pci_map_irq = noname_map_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .pci_swizzle = common_swizzle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .sys = { .sio = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* For UDB, the only available PCI slot must not map to IRQ 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) since that's the builtin MSS sound chip. That PCI slot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) will map to PIRQ1 (for INTA at least), so we give it IRQ 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) Unfortunately we have to do this for NONAME as well, since
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) they are co-indicated when the platform type "Noname" is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) selected... :-( */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .route_tab = 0x0b0a0f0d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) ALIAS_MV(noname)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_P2K)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct alpha_machine_vector p2k_mv __initmv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .vector_name = "Platform2000",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) DO_EV4_MMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) DO_DEFAULT_RTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) DO_LCA_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .machine_check = lca_machine_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .min_io_address = DEFAULT_IO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .nr_irqs = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .device_interrupt = srm_device_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .init_arch = lca_init_arch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .init_irq = sio_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .init_rtc = common_init_rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .init_pci = noname_init_pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .kill_arch = sio_kill_arch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .pci_map_irq = p2k_map_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .pci_swizzle = common_swizzle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .sys = { .sio = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .route_tab = 0x0b0a090f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) ALIAS_MV(p2k)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_XL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) struct alpha_machine_vector xl_mv __initmv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .vector_name = "XL",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) DO_EV4_MMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) DO_DEFAULT_RTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) DO_APECS_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .machine_check = apecs_machine_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .max_isa_dma_address = ALPHA_XL_MAX_ISA_DMA_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .min_io_address = DEFAULT_IO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .min_mem_address = XL_DEFAULT_MEM_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .nr_irqs = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .device_interrupt = isa_device_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .init_arch = apecs_init_arch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .init_irq = sio_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .init_rtc = common_init_rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .init_pci = noname_init_pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .kill_arch = sio_kill_arch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .pci_map_irq = noname_map_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .pci_swizzle = common_swizzle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .sys = { .sio = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .route_tab = 0x0b0a090f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) ALIAS_MV(xl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags