^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/alpha/kernel/sys_sable.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1995 David A Rusling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 1996 Jay A Estabrook
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 1998, 1999 Richard Henderson
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Code supporting the Sable, Sable-Gamma, and Lynx systems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/mmu_context.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/core_t2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/tlbflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "proto.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "irq_impl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "pci_impl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "machvec_impl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) DEFINE_SPINLOCK(sable_lynx_irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) typedef struct irq_swizzle_struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) char irq_to_mask[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) char mask_to_irq[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* Note mask bit is true for DISABLED irqs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) unsigned long shadow_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) void (*update_irq_hw)(unsigned long bit, unsigned long mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) void (*ack_irq_hw)(unsigned long bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) } irq_swizzle_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static irq_swizzle_t *sable_lynx_irq_swizzle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static void sable_lynx_init_irq(int nr_of_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_SABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /***********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * For SABLE, which is really baroque, we manage 40 IRQ's, but the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * hardware really only supports 24, not via normal ISA PIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * but cascaded custom 8259's, etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * 0-7 (char at 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * 8-15 (char at 53a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * 16-23 (char at 53c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * Summary Registers (536/53a/53c):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * Bit Meaning Kernel IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) *------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * 0 PCI slot 0 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * 1 NCR810 (builtin) 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * 2 TULIP (builtin) 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * 3 mouse 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * 4 PCI slot 1 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * 5 PCI slot 2 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * 6 keyboard 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * 7 floppy 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * 8 COM2 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * 9 parallel port 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) *10 EISA irq 3 -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) *11 EISA irq 4 -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) *12 EISA irq 5 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) *13 EISA irq 6 -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) *14 EISA irq 7 -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) *15 COM1 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) *16 EISA irq 9 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) *17 EISA irq 10 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) *18 EISA irq 11 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) *19 EISA irq 12 -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) *20 EISA irq 13 -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) *21 EISA irq 14 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) *22 NC 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) *23 IIC -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) sable_update_irq_hw(unsigned long bit, unsigned long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int port = 0x537;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (bit >= 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) port = 0x53d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) mask >>= 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) } else if (bit >= 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) port = 0x53b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) mask >>= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) outb(mask, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) sable_ack_irq_hw(unsigned long bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) int port, val1, val2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (bit >= 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) port = 0x53c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) val1 = 0xE0 | (bit - 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) val2 = 0xE0 | 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) } else if (bit >= 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) port = 0x53a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) val1 = 0xE0 | (bit - 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) val2 = 0xE0 | 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) port = 0x536;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) val1 = 0xE0 | (bit - 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) val2 = 0xE0 | 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) outb(val1, port); /* ack the slave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) outb(val2, 0x534); /* ack the master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static irq_swizzle_t sable_irq_swizzle = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) -1, 6, -1, 8, 15, 12, 7, 9, /* pseudo PIC 0-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) -1, 16, 17, 18, 3, -1, 21, 22, /* pseudo PIC 8-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) -1, -1, -1, -1, -1, -1, -1, -1, /* pseudo EISA 0-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) -1, -1, -1, -1, -1, -1, -1, -1, /* pseudo EISA 8-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 2, 1, 0, 4, 5, -1, -1, -1, /* pseudo PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) -1, -1, -1, -1, -1, -1, -1, -1, /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) -1, -1, -1, -1, -1, -1, -1, -1, /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) -1, -1, -1, -1, -1, -1, -1, -1 /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 34, 33, 32, 12, 35, 36, 1, 6, /* mask 0-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 3, 7, -1, -1, 5, -1, -1, 4, /* mask 8-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 9, 10, 11, -1, -1, 14, 15, -1, /* mask 16-23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) -1, -1, -1, -1, -1, -1, -1, -1, /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) -1, -1, -1, -1, -1, -1, -1, -1, /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) -1, -1, -1, -1, -1, -1, -1, -1, /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) -1, -1, -1, -1, -1, -1, -1, -1, /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) -1, -1, -1, -1, -1, -1, -1, -1 /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) sable_update_irq_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) sable_ack_irq_hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) sable_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) outb(-1, 0x537); /* slave 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) outb(-1, 0x53b); /* slave 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) outb(-1, 0x53d); /* slave 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) outb(0x44, 0x535); /* enable cascades in master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) sable_lynx_irq_swizzle = &sable_irq_swizzle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) sable_lynx_init_irq(40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * PCI Fixup configuration for ALPHA SABLE (2100).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * The device to slot mapping looks like:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * Slot Device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * 0 TULIP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * 1 SCSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * 2 PCI-EISA bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * 3 none
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * 4 none
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * 5 none
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * 6 PCI on board slot 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * 7 PCI on board slot 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * 8 PCI on board slot 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * This two layered interrupt approach means that we allocate IRQ 16 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * above for PCI interrupts. The IRQ relates to which bit the interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * comes in on. This makes interrupt processing much easier.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * NOTE: the IRQ assignments below are arbitrary, but need to be consistent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * with the values in the irq swizzling tables above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) sable_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static char irq_tab[9][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /*INT INTA INTB INTC INTD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) { 32+0, 32+0, 32+0, 32+0, 32+0}, /* IdSel 0, TULIP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) { 32+1, 32+1, 32+1, 32+1, 32+1}, /* IdSel 1, SCSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) { -1, -1, -1, -1, -1}, /* IdSel 2, SIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) { -1, -1, -1, -1, -1}, /* IdSel 3, none */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) { -1, -1, -1, -1, -1}, /* IdSel 4, none */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) { -1, -1, -1, -1, -1}, /* IdSel 5, none */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) { 32+2, 32+2, 32+2, 32+2, 32+2}, /* IdSel 6, slot 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) { 32+3, 32+3, 32+3, 32+3, 32+3}, /* IdSel 7, slot 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) { 32+4, 32+4, 32+4, 32+4, 32+4} /* IdSel 8, slot 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) long min_idsel = 0, max_idsel = 8, irqs_per_slot = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return COMMON_TABLE_LOOKUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #endif /* defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_SABLE) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_LYNX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /***********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* LYNX hardware specifics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * For LYNX, which is also baroque, we manage 64 IRQs, via a custom IC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * Bit Meaning Kernel IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) *------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * 3 mouse 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * 6 keyboard 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * 7 floppy 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * 8 COM2 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * 9 parallel port 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) *10 EISA irq 3 -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) *11 EISA irq 4 -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) *12 EISA irq 5 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) *13 EISA irq 6 -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) *14 EISA irq 7 -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) *15 COM1 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) *16 EISA irq 9 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) *17 EISA irq 10 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) *18 EISA irq 11 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) *19 EISA irq 12 -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) *20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) *21 EISA irq 14 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) *22 EISA irq 15 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) *23 IIC -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) *24 VGA (builtin) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) *25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) *26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) *27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) *28 NCR810 (builtin) 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) *29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) *30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) *31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) *32 PCI 0 slot 4 A primary bus 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) *33 PCI 0 slot 4 B primary bus 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) *34 PCI 0 slot 4 C primary bus 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) *35 PCI 0 slot 4 D primary bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) *36 PCI 0 slot 5 A primary bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) *37 PCI 0 slot 5 B primary bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) *38 PCI 0 slot 5 C primary bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) *39 PCI 0 slot 5 D primary bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) *40 PCI 0 slot 6 A primary bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) *41 PCI 0 slot 6 B primary bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) *42 PCI 0 slot 6 C primary bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) *43 PCI 0 slot 6 D primary bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) *44 PCI 0 slot 7 A primary bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) *45 PCI 0 slot 7 B primary bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) *46 PCI 0 slot 7 C primary bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) *47 PCI 0 slot 7 D primary bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) *48 PCI 0 slot 0 A secondary bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) *49 PCI 0 slot 0 B secondary bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) *50 PCI 0 slot 0 C secondary bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) *51 PCI 0 slot 0 D secondary bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) *52 PCI 0 slot 1 A secondary bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) *53 PCI 0 slot 1 B secondary bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) *54 PCI 0 slot 1 C secondary bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) *55 PCI 0 slot 1 D secondary bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) *56 PCI 0 slot 2 A secondary bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) *57 PCI 0 slot 2 B secondary bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) *58 PCI 0 slot 2 C secondary bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) *59 PCI 0 slot 2 D secondary bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) *60 PCI 0 slot 3 A secondary bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) *61 PCI 0 slot 3 B secondary bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) *62 PCI 0 slot 3 C secondary bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) *63 PCI 0 slot 3 D secondary bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) lynx_update_irq_hw(unsigned long bit, unsigned long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * Write the AIR register on the T3/T4 with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * address of the IC mask register (offset 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) *(vulp)T2_AIR = 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) *(vulp)T2_AIR; /* re-read to force write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) *(vulp)T2_DIR = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) lynx_ack_irq_hw(unsigned long bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) *(vulp)T2_VAR = (u_long) bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static irq_swizzle_t lynx_irq_swizzle = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) { /* irq_to_mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) -1, 6, -1, 8, 15, 12, 7, 9, /* pseudo PIC 0-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) -1, 16, 17, 18, 3, -1, 21, 22, /* pseudo PIC 8-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) -1, -1, -1, -1, -1, -1, -1, -1, /* pseudo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) -1, -1, -1, -1, 28, -1, -1, -1, /* pseudo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 32, 33, 34, 35, 36, 37, 38, 39, /* mask 32-39 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 40, 41, 42, 43, 44, 45, 46, 47, /* mask 40-47 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 48, 49, 50, 51, 52, 53, 54, 55, /* mask 48-55 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 56, 57, 58, 59, 60, 61, 62, 63 /* mask 56-63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) { /* mask_to_irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) -1, -1, -1, 12, -1, -1, 1, 6, /* mask 0-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 3, 7, -1, -1, 5, -1, -1, 4, /* mask 8-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 9, 10, 11, -1, -1, 14, 15, -1, /* mask 16-23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) -1, -1, -1, -1, 28, -1, -1, -1, /* mask 24-31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 32, 33, 34, 35, 36, 37, 38, 39, /* mask 32-39 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 40, 41, 42, 43, 44, 45, 46, 47, /* mask 40-47 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 48, 49, 50, 51, 52, 53, 54, 55, /* mask 48-55 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 56, 57, 58, 59, 60, 61, 62, 63 /* mask 56-63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) lynx_update_irq_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) lynx_ack_irq_hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) lynx_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) sable_lynx_irq_swizzle = &lynx_irq_swizzle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) sable_lynx_init_irq(64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * PCI Fixup configuration for ALPHA LYNX (2100A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * The device to slot mapping looks like:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * Slot Device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * 0 none
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * 1 none
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * 2 PCI-EISA bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * 3 PCI-PCI bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * 4 NCR 810 (Demi-Lynx only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * 5 none
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * 6 PCI on board slot 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * 7 PCI on board slot 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * 8 PCI on board slot 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * 9 PCI on board slot 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * And behind the PPB we have:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * 11 PCI on board slot 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * 12 PCI on board slot 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * 13 PCI on board slot 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * 14 PCI on board slot 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * NOTE: the IRQ assignments below are arbitrary, but need to be consistent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * with the values in the irq swizzling tables above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) lynx_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static char irq_tab[19][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /*INT INTA INTB INTC INTD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) { -1, -1, -1, -1, -1}, /* IdSel 13, PCEB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) { -1, -1, -1, -1, -1}, /* IdSel 14, PPB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) { 28, 28, 28, 28, 28}, /* IdSel 15, NCR demi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) { -1, -1, -1, -1, -1}, /* IdSel 16, none */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) { 32, 32, 33, 34, 35}, /* IdSel 17, slot 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) { 36, 36, 37, 38, 39}, /* IdSel 18, slot 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) { 40, 40, 41, 42, 43}, /* IdSel 19, slot 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) { 44, 44, 45, 46, 47}, /* IdSel 20, slot 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) { -1, -1, -1, -1, -1}, /* IdSel 22, none */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* The following are actually behind the PPB. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) { -1, -1, -1, -1, -1}, /* IdSel 16 none */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) { 28, 28, 28, 28, 28}, /* IdSel 17 NCR lynx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) { -1, -1, -1, -1, -1}, /* IdSel 18 none */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) { -1, -1, -1, -1, -1}, /* IdSel 19 none */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) { -1, -1, -1, -1, -1}, /* IdSel 20 none */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) { -1, -1, -1, -1, -1}, /* IdSel 21 none */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) { 48, 48, 49, 50, 51}, /* IdSel 22 slot 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) { 52, 52, 53, 54, 55}, /* IdSel 23 slot 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) { 56, 56, 57, 58, 59}, /* IdSel 24 slot 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) { 60, 60, 61, 62, 63} /* IdSel 25 slot 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) const long min_idsel = 2, max_idsel = 20, irqs_per_slot = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return COMMON_TABLE_LOOKUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static u8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) lynx_swizzle(struct pci_dev *dev, u8 *pinp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) int slot, pin = *pinp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (dev->bus->number == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) slot = PCI_SLOT(dev->devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /* Check for the built-in bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) else if (PCI_SLOT(dev->bus->self->devfn) == 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) slot = PCI_SLOT(dev->devfn) + 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* Must be a card-based bridge. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (PCI_SLOT(dev->bus->self->devfn) == 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) slot = PCI_SLOT(dev->devfn) + 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) pin = pci_swizzle_interrupt_pin(dev, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* Move up the chain of bridges. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) dev = dev->bus->self;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* Slot of the next bridge. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) slot = PCI_SLOT(dev->devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) } while (dev->bus->self);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) *pinp = pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #endif /* defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_LYNX) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /***********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /* GENERIC irq routines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) sable_lynx_enable_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) unsigned long bit, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) bit = sable_lynx_irq_swizzle->irq_to_mask[d->irq];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) spin_lock(&sable_lynx_irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) mask = sable_lynx_irq_swizzle->shadow_mask &= ~(1UL << bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) sable_lynx_irq_swizzle->update_irq_hw(bit, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) spin_unlock(&sable_lynx_irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) printk("%s: mask 0x%lx bit 0x%lx irq 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) __func__, mask, bit, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) sable_lynx_disable_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) unsigned long bit, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) bit = sable_lynx_irq_swizzle->irq_to_mask[d->irq];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) spin_lock(&sable_lynx_irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) mask = sable_lynx_irq_swizzle->shadow_mask |= 1UL << bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) sable_lynx_irq_swizzle->update_irq_hw(bit, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) spin_unlock(&sable_lynx_irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) printk("%s: mask 0x%lx bit 0x%lx irq 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) __func__, mask, bit, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) sable_lynx_mask_and_ack_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) unsigned long bit, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) bit = sable_lynx_irq_swizzle->irq_to_mask[d->irq];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) spin_lock(&sable_lynx_irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) mask = sable_lynx_irq_swizzle->shadow_mask |= 1UL << bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) sable_lynx_irq_swizzle->update_irq_hw(bit, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) sable_lynx_irq_swizzle->ack_irq_hw(bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) spin_unlock(&sable_lynx_irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static struct irq_chip sable_lynx_irq_type = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .name = "SABLE/LYNX",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .irq_unmask = sable_lynx_enable_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .irq_mask = sable_lynx_disable_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .irq_mask_ack = sable_lynx_mask_and_ack_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) sable_lynx_srm_device_interrupt(unsigned long vector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /* Note that the vector reported by the SRM PALcode corresponds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) to the interrupt mask bits, but we have to manage via the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) so-called legacy IRQs for many common devices. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) int bit, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) bit = (vector - 0x800) >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) irq = sable_lynx_irq_swizzle->mask_to_irq[bit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) printk("%s: vector 0x%lx bit 0x%x irq 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) __func__, vector, bit, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) handle_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) sable_lynx_init_irq(int nr_of_irqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) long i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) for (i = 0; i < nr_of_irqs; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) irq_set_chip_and_handler(i, &sable_lynx_irq_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) irq_set_status_flags(i, IRQ_LEVEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) common_init_isa_dma();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) sable_lynx_init_pci(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) common_init_pci();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) /*****************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * The System Vectors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) * In order that T2_HAE_ADDRESS should be a constant, we play
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) * these games with GAMMA_BIAS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #if defined(CONFIG_ALPHA_GENERIC) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) (defined(CONFIG_ALPHA_SABLE) && !defined(CONFIG_ALPHA_GAMMA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #undef GAMMA_BIAS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define GAMMA_BIAS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct alpha_machine_vector sable_mv __initmv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .vector_name = "Sable",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) DO_EV4_MMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) DO_DEFAULT_RTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) DO_T2_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .machine_check = t2_machine_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .max_isa_dma_address = ALPHA_SABLE_MAX_ISA_DMA_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .min_io_address = EISA_DEFAULT_IO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .min_mem_address = T2_DEFAULT_MEM_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .nr_irqs = 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .device_interrupt = sable_lynx_srm_device_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .init_arch = t2_init_arch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .init_irq = sable_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .init_rtc = common_init_rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .init_pci = sable_lynx_init_pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .kill_arch = t2_kill_arch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .pci_map_irq = sable_map_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .pci_swizzle = common_swizzle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .sys = { .t2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .gamma_bias = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) } }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) ALIAS_MV(sable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #endif /* GENERIC || (SABLE && !GAMMA) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #if defined(CONFIG_ALPHA_GENERIC) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) (defined(CONFIG_ALPHA_SABLE) && defined(CONFIG_ALPHA_GAMMA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #undef GAMMA_BIAS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define GAMMA_BIAS _GAMMA_BIAS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) struct alpha_machine_vector sable_gamma_mv __initmv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .vector_name = "Sable-Gamma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) DO_EV5_MMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) DO_DEFAULT_RTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) DO_T2_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .machine_check = t2_machine_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .max_isa_dma_address = ALPHA_SABLE_MAX_ISA_DMA_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .min_io_address = EISA_DEFAULT_IO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .min_mem_address = T2_DEFAULT_MEM_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .nr_irqs = 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .device_interrupt = sable_lynx_srm_device_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .init_arch = t2_init_arch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .init_irq = sable_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .init_rtc = common_init_rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .init_pci = sable_lynx_init_pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .kill_arch = t2_kill_arch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .pci_map_irq = sable_map_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .pci_swizzle = common_swizzle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .sys = { .t2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .gamma_bias = _GAMMA_BIAS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) } }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) ALIAS_MV(sable_gamma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #endif /* GENERIC || (SABLE && GAMMA) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_LYNX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #undef GAMMA_BIAS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define GAMMA_BIAS _GAMMA_BIAS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct alpha_machine_vector lynx_mv __initmv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .vector_name = "Lynx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) DO_EV4_MMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) DO_DEFAULT_RTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) DO_T2_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .machine_check = t2_machine_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .max_isa_dma_address = ALPHA_SABLE_MAX_ISA_DMA_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .min_io_address = EISA_DEFAULT_IO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .min_mem_address = T2_DEFAULT_MEM_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .nr_irqs = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .device_interrupt = sable_lynx_srm_device_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .init_arch = t2_init_arch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .init_irq = lynx_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .init_rtc = common_init_rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .init_pci = sable_lynx_init_pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .kill_arch = t2_kill_arch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .pci_map_irq = lynx_map_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .pci_swizzle = lynx_swizzle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .sys = { .t2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .gamma_bias = _GAMMA_BIAS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) } }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) ALIAS_MV(lynx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #endif /* GENERIC || LYNX */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags