^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/alpha/kernel/sys_rx164.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1995 David A Rusling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 1996 Jay A Estabrook
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 1998, 1999 Richard Henderson
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Code supporting the RX164 (PCA56+POLARIS).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/mmu_context.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/core_polaris.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/tlbflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "proto.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "irq_impl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "pci_impl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "machvec_impl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* Note mask bit is true for ENABLED irqs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static unsigned long cached_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) rx164_update_irq_hw(unsigned long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) volatile unsigned int *irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) irq_mask = (void *)(POLARIS_DENSE_CONFIG_BASE + 0x74);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) *irq_mask = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) *irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) rx164_enable_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) rx164_update_irq_hw(cached_irq_mask |= 1UL << (d->irq - 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) rx164_disable_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) rx164_update_irq_hw(cached_irq_mask &= ~(1UL << (d->irq - 16)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static struct irq_chip rx164_irq_type = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .name = "RX164",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .irq_unmask = rx164_enable_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .irq_mask = rx164_disable_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .irq_mask_ack = rx164_disable_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) rx164_device_interrupt(unsigned long vector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) unsigned long pld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) volatile unsigned int *dirr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) long i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* Read the interrupt summary register. On Polaris, this is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) the DIRR register in PCI config space (offset 0x84). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) dirr = (void *)(POLARIS_DENSE_CONFIG_BASE + 0x84);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) pld = *dirr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * Now for every possible bit set, work through them and call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * the appropriate interrupt handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) while (pld) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) i = ffz(~pld);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) pld &= pld - 1; /* clear least bit set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (i == 20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) isa_no_iack_sc_device_interrupt(vector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) handle_irq(16+i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) rx164_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) long i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) rx164_update_irq_hw(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) for (i = 16; i < 40; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) irq_set_chip_and_handler(i, &rx164_irq_type, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) irq_set_status_flags(i, IRQ_LEVEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) init_i8259a_irqs();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) common_init_isa_dma();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (request_irq(16 + 20, no_action, 0, "isa-cascade", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) pr_err("Failed to register isa-cascade interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * The RX164 changed its interrupt routing between pass1 and pass2...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * PASS1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * Slot IDSEL INTA INTB INTC INTD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * 0 6 5 10 15 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * 1 7 4 9 14 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * 2 5 3 8 13 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * 3 9 2 7 12 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * 4 10 1 6 11 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * PASS2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * Slot IDSEL INTA INTB INTC INTD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * 0 5 1 7 12 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * 1 6 2 8 13 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * 2 8 3 9 14 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * 3 9 4 10 15 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * 4 10 5 11 16 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * IdSel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * 5 32 bit PCI option slot 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * 6 64 bit PCI option slot 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * 7 PCI-ISA bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * 7 64 bit PCI option slot 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * 9 32 bit PCI option slot 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * 10 PCI-PCI bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) rx164_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static char irq_tab_pass1[6][5] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /*INT INTA INTB INTC INTD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) { 16+3, 16+3, 16+8, 16+13, 16+18}, /* IdSel 5, slot 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) { 16+5, 16+5, 16+10, 16+15, 16+20}, /* IdSel 6, slot 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) { 16+4, 16+4, 16+9, 16+14, 16+19}, /* IdSel 7, slot 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) { -1, -1, -1, -1, -1}, /* IdSel 8, PCI/ISA bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) { 16+2, 16+2, 16+7, 16+12, 16+17}, /* IdSel 9, slot 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) { 16+1, 16+1, 16+6, 16+11, 16+16}, /* IdSel 10, slot 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static char irq_tab[6][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /*INT INTA INTB INTC INTD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) { 16+0, 16+0, 16+6, 16+11, 16+16}, /* IdSel 5, slot 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) { 16+1, 16+1, 16+7, 16+12, 16+17}, /* IdSel 6, slot 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) { -1, -1, -1, -1, -1}, /* IdSel 7, PCI/ISA bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) { 16+2, 16+2, 16+8, 16+13, 16+18}, /* IdSel 8, slot 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) { 16+3, 16+3, 16+9, 16+14, 16+19}, /* IdSel 9, slot 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) { 16+4, 16+4, 16+10, 16+15, 16+5}, /* IdSel 10, PCI-PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) const long min_idsel = 5, max_idsel = 10, irqs_per_slot = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* JRP - Need to figure out how to distinguish pass1 from pass2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) and use the correct table. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return COMMON_TABLE_LOOKUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * The System Vector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct alpha_machine_vector rx164_mv __initmv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .vector_name = "RX164",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) DO_EV5_MMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) DO_DEFAULT_RTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) DO_POLARIS_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .machine_check = polaris_machine_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .min_io_address = DEFAULT_IO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .min_mem_address = DEFAULT_MEM_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .nr_irqs = 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .device_interrupt = rx164_device_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .init_arch = polaris_init_arch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .init_irq = rx164_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .init_rtc = common_init_rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .init_pci = common_init_pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .kill_arch = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .pci_map_irq = rx164_map_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .pci_swizzle = common_swizzle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) ALIAS_MV(rx164)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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