^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/alpha/kernel/sys_ruffian.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1995 David A Rusling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 1996 Jay A Estabrook
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 1998, 1999, 2000 Richard Henderson
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Code supporting the RUFFIAN.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/timex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/mmu_context.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/core_cia.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/tlbflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "proto.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "irq_impl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "pci_impl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include "machvec_impl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) ruffian_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* Invert 6&7 for i82371 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) *(vulp)PYXIS_INT_HILO = 0x000000c0UL; mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) *(vulp)PYXIS_INT_CNFG = 0x00002064UL; mb(); /* all clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) outb(0x11,0xA0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) outb(0x08,0xA1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) outb(0x02,0xA1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) outb(0x01,0xA1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) outb(0xFF,0xA1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) outb(0x11,0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) outb(0x00,0x21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) outb(0x04,0x21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) outb(0x01,0x21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) outb(0xFF,0x21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* Finish writing the 82C59A PIC Operation Control Words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) outb(0x20,0xA0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) outb(0x20,0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) init_i8259a_irqs();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* Not interested in the bogus interrupts (0,3,6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) NMI (1), HALT (2), flash (5), or 21142 (8). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) init_pyxis_irqs(0x16f0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) common_init_isa_dma();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define RUFFIAN_LATCH DIV_ROUND_CLOSEST(PIT_TICK_RATE, HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) ruffian_init_rtc(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* Ruffian does not have the RTC connected to the CPU timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) interrupt. Instead, it uses the PIT connected to IRQ 0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Setup interval timer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) outb(0x34, 0x43); /* binary, mode 2, LSB/MSB, ch 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) outb(RUFFIAN_LATCH & 0xff, 0x40); /* LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) outb(RUFFIAN_LATCH >> 8, 0x40); /* MSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) outb(0xb6, 0x43); /* pit counter 2: speaker */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) outb(0x31, 0x42);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) outb(0x13, 0x42);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (request_irq(0, rtc_timer_interrupt, 0, "timer", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) pr_err("Failed to request irq 0 (timer)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) ruffian_kill_arch (int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) cia_kill_arch(mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* This only causes re-entry to ARCSBIOS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* Perhaps this works for other PYXIS as well? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) *(vuip) PYXIS_RESET = 0x0000dead;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * Interrupt routing:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * Primary bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * IdSel INTA INTB INTC INTD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * 21052 13 - - - -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * SIO 14 23 - - -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * 21143 15 44 - - -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * Slot 0 17 43 42 41 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * Secondary bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * IdSel INTA INTB INTC INTD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * Slot 0 8 (18) 19 18 17 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * Slot 1 9 (19) 31 30 29 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * Slot 2 10 (20) 27 26 25 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * Slot 3 11 (21) 39 38 37 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * Slot 4 12 (22) 35 34 33 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * 53c875 13 (23) 20 - - -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) ruffian_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static char irq_tab[11][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /*INT INTA INTB INTC INTD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {-1, -1, -1, -1, -1}, /* IdSel 13, 21052 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {-1, -1, -1, -1, -1}, /* IdSel 14, SIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {44, 44, 44, 44, 44}, /* IdSel 15, 21143 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {-1, -1, -1, -1, -1}, /* IdSel 16, none */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {43, 43, 42, 41, 40}, /* IdSel 17, 64-bit slot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* the next 6 are actually on PCI bus 1, across the bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {19, 19, 18, 17, 16}, /* IdSel 8, slot 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {31, 31, 30, 29, 28}, /* IdSel 9, slot 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {27, 27, 26, 25, 24}, /* IdSel 10, slot 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {39, 39, 38, 37, 36}, /* IdSel 11, slot 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {35, 35, 34, 33, 32}, /* IdSel 12, slot 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {20, 20, 20, 20, 20}, /* IdSel 13, 53c875 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) const long min_idsel = 13, max_idsel = 23, irqs_per_slot = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return COMMON_TABLE_LOOKUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static u8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) ruffian_swizzle(struct pci_dev *dev, u8 *pinp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) int slot, pin = *pinp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (dev->bus->number == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) slot = PCI_SLOT(dev->devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* Check for the built-in bridge. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) else if (PCI_SLOT(dev->bus->self->devfn) == 13) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) slot = PCI_SLOT(dev->devfn) + 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* Must be a card-based bridge. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (PCI_SLOT(dev->bus->self->devfn) == 13) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) slot = PCI_SLOT(dev->devfn) + 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) pin = pci_swizzle_interrupt_pin(dev, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* Move up the chain of bridges. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) dev = dev->bus->self;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* Slot of the next bridge. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) slot = PCI_SLOT(dev->devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) } while (dev->bus->self);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) *pinp = pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #ifdef BUILDING_FOR_MILO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * The DeskStation Ruffian motherboard firmware does not place
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * the memory size in the PALimpure area. Therefore, we use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * the Bank Configuration Registers in PYXIS to obtain the size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static unsigned long __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ruffian_get_bank_size(unsigned long offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) unsigned long bank_addr, bank, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* Valid offsets are: 0x800, 0x840 and 0x880
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) since Ruffian only uses three banks. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) bank_addr = (unsigned long)PYXIS_MCR + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) bank = *(vulp)bank_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* Check BANK_ENABLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (bank & 0x01) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static unsigned long size[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 0x40000000UL, /* 0x00, 1G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 0x20000000UL, /* 0x02, 512M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 0x10000000UL, /* 0x04, 256M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 0x08000000UL, /* 0x06, 128M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 0x04000000UL, /* 0x08, 64M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 0x02000000UL, /* 0x0a, 32M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 0x01000000UL, /* 0x0c, 16M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 0x00800000UL, /* 0x0e, 8M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 0x80000000UL, /* 0x10, 2G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) bank = (bank & 0x1e) >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (bank < ARRAY_SIZE(size))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) ret = size[bank];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #endif /* BUILDING_FOR_MILO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * The System Vector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct alpha_machine_vector ruffian_mv __initmv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .vector_name = "Ruffian",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) DO_EV5_MMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) DO_DEFAULT_RTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) DO_PYXIS_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .machine_check = cia_machine_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .max_isa_dma_address = ALPHA_RUFFIAN_MAX_ISA_DMA_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .min_io_address = DEFAULT_IO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .min_mem_address = DEFAULT_MEM_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .pci_dac_offset = PYXIS_DAC_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .nr_irqs = 48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .device_interrupt = pyxis_device_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .init_arch = pyxis_init_arch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .init_irq = ruffian_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .init_rtc = ruffian_init_rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .init_pci = cia_init_pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .kill_arch = ruffian_kill_arch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .pci_map_irq = ruffian_map_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .pci_swizzle = ruffian_swizzle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) ALIAS_MV(ruffian)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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