^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/alpha/kernel/sys_rawhide.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1995 David A Rusling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 1996 Jay A Estabrook
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 1998, 1999 Richard Henderson
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Code supporting the RAWHIDE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/mmu_context.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/core_mcpcia.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/tlbflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "proto.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "irq_impl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "pci_impl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "machvec_impl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * HACK ALERT! only the boot cpu is used for interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* Note mask bit is true for ENABLED irqs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static unsigned int hose_irq_masks[4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 0xff0000, 0xfe0000, 0xff0000, 0xff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static unsigned int cached_irq_masks[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) DEFINE_SPINLOCK(rawhide_irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) rawhide_update_irq_hw(int hose, int mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) *(vuip)MCPCIA_INT_MASK0(MCPCIA_HOSE2MID(hose)) = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) *(vuip)MCPCIA_INT_MASK0(MCPCIA_HOSE2MID(hose));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define hose_exists(h) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) (((h) < MCPCIA_MAX_HOSES) && (cached_irq_masks[(h)] != 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) rawhide_enable_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) unsigned int mask, hose;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unsigned int irq = d->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) irq -= 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) hose = irq / 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) if (!hose_exists(hose)) /* if hose non-existent, exit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) irq -= hose * 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) mask = 1 << irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) spin_lock(&rawhide_irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) mask |= cached_irq_masks[hose];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) cached_irq_masks[hose] = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) rawhide_update_irq_hw(hose, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) spin_unlock(&rawhide_irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) rawhide_disable_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) unsigned int mask, hose;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) unsigned int irq = d->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) irq -= 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) hose = irq / 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (!hose_exists(hose)) /* if hose non-existent, exit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) irq -= hose * 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) mask = ~(1 << irq) | hose_irq_masks[hose];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) spin_lock(&rawhide_irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) mask &= cached_irq_masks[hose];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) cached_irq_masks[hose] = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) rawhide_update_irq_hw(hose, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) spin_unlock(&rawhide_irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) rawhide_mask_and_ack_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) unsigned int mask, mask1, hose;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) unsigned int irq = d->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) irq -= 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) hose = irq / 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (!hose_exists(hose)) /* if hose non-existent, exit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) irq -= hose * 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) mask1 = 1 << irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) mask = ~mask1 | hose_irq_masks[hose];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) spin_lock(&rawhide_irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) mask &= cached_irq_masks[hose];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) cached_irq_masks[hose] = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) rawhide_update_irq_hw(hose, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* Clear the interrupt. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) *(vuip)MCPCIA_INT_REQ(MCPCIA_HOSE2MID(hose)) = mask1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) spin_unlock(&rawhide_irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static struct irq_chip rawhide_irq_type = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .name = "RAWHIDE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .irq_unmask = rawhide_enable_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .irq_mask = rawhide_disable_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .irq_mask_ack = rawhide_mask_and_ack_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) rawhide_srm_device_interrupt(unsigned long vector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) irq = (vector - 0x800) >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * The RAWHIDE SRM console reports PCI interrupts with a vector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * 0x80 *higher* than one might expect, as PCI IRQ 0 (ie bit 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * shows up as IRQ 24, etc, etc. We adjust it down by 8 to have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * it line up with the actual bit numbers from the REQ registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * which is how we manage the interrupts/mask. Sigh...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * Also, PCI #1 interrupts are offset some more... :-(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (irq == 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* SCSI on PCI1 is special. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) irq = 72;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* Adjust by which hose it is from. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) irq -= ((irq + 16) >> 2) & 0x38;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) handle_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) rawhide_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct pci_controller *hose;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) long i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) mcpcia_init_hoses();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* Clear them all; only hoses that exist will be non-zero. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) for (i = 0; i < MCPCIA_MAX_HOSES; i++) cached_irq_masks[i] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) for (hose = hose_head; hose; hose = hose->next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) unsigned int h = hose->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) unsigned int mask = hose_irq_masks[h];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) cached_irq_masks[h] = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) *(vuip)MCPCIA_INT_MASK0(MCPCIA_HOSE2MID(h)) = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) *(vuip)MCPCIA_INT_MASK1(MCPCIA_HOSE2MID(h)) = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) for (i = 16; i < 128; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) irq_set_chip_and_handler(i, &rawhide_irq_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) irq_set_status_flags(i, IRQ_LEVEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) init_i8259a_irqs();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) common_init_isa_dma();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * PCI Fixup configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * Summary @ MCPCIA_PCI0_INT_REQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * Bit Meaning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * 0 Interrupt Line A from slot 2 PCI0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * 1 Interrupt Line B from slot 2 PCI0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * 2 Interrupt Line C from slot 2 PCI0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * 3 Interrupt Line D from slot 2 PCI0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * 4 Interrupt Line A from slot 3 PCI0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * 5 Interrupt Line B from slot 3 PCI0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * 6 Interrupt Line C from slot 3 PCI0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * 7 Interrupt Line D from slot 3 PCI0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * 8 Interrupt Line A from slot 4 PCI0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * 9 Interrupt Line B from slot 4 PCI0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * 10 Interrupt Line C from slot 4 PCI0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * 11 Interrupt Line D from slot 4 PCI0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * 12 Interrupt Line A from slot 5 PCI0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * 13 Interrupt Line B from slot 5 PCI0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * 14 Interrupt Line C from slot 5 PCI0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * 15 Interrupt Line D from slot 5 PCI0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * 16 EISA interrupt (PCI 0) or SCSI interrupt (PCI 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * 17-23 NA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * IdSel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * 1 EISA bridge (PCI bus 0 only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * 2 PCI option slot 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * 3 PCI option slot 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * 4 PCI option slot 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * 5 PCI option slot 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) rawhide_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static char irq_tab[5][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /*INT INTA INTB INTC INTD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) { 16+16, 16+16, 16+16, 16+16, 16+16}, /* IdSel 1 SCSI PCI 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) { 16+ 0, 16+ 0, 16+ 1, 16+ 2, 16+ 3}, /* IdSel 2 slot 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) { 16+ 4, 16+ 4, 16+ 5, 16+ 6, 16+ 7}, /* IdSel 3 slot 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) { 16+ 8, 16+ 8, 16+ 9, 16+10, 16+11}, /* IdSel 4 slot 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) { 16+12, 16+12, 16+13, 16+14, 16+15} /* IdSel 5 slot 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) const long min_idsel = 1, max_idsel = 5, irqs_per_slot = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct pci_controller *hose = dev->sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) int irq = COMMON_TABLE_LOOKUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (irq >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) irq += 24 * hose->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * The System Vector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct alpha_machine_vector rawhide_mv __initmv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .vector_name = "Rawhide",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) DO_EV5_MMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) DO_DEFAULT_RTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) DO_MCPCIA_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .machine_check = mcpcia_machine_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .min_io_address = DEFAULT_IO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .min_mem_address = MCPCIA_DEFAULT_MEM_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .pci_dac_offset = MCPCIA_DAC_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .nr_irqs = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .device_interrupt = rawhide_srm_device_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .init_arch = mcpcia_init_arch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .init_irq = rawhide_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .init_rtc = common_init_rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .init_pci = common_init_pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .kill_arch = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .pci_map_irq = rawhide_map_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .pci_swizzle = common_swizzle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) ALIAS_MV(rawhide)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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