Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *	linux/arch/alpha/kernel/sys_mikasa.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *	Copyright (C) 1995 David A Rusling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *	Copyright (C) 1996 Jay A Estabrook
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *	Copyright (C) 1998, 1999 Richard Henderson
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Code supporting the MIKASA (AlphaServer 1000).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <asm/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <asm/mce.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <asm/dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <asm/mmu_context.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <asm/core_apecs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <asm/core_cia.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <asm/tlbflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include "proto.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #include "irq_impl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #include "pci_impl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #include "machvec_impl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) /* Note mask bit is true for ENABLED irqs.  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) static int cached_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) mikasa_update_irq_hw(int mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	outw(mask, 0x536);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) mikasa_enable_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	mikasa_update_irq_hw(cached_irq_mask |= 1 << (d->irq - 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) mikasa_disable_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	mikasa_update_irq_hw(cached_irq_mask &= ~(1 << (d->irq - 16)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) static struct irq_chip mikasa_irq_type = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	.name		= "MIKASA",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	.irq_unmask	= mikasa_enable_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	.irq_mask	= mikasa_disable_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	.irq_mask_ack	= mikasa_disable_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) static void 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) mikasa_device_interrupt(unsigned long vector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	unsigned long pld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	/* Read the interrupt summary registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	pld = (((~inw(0x534) & 0x0000ffffUL) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	       | (((unsigned long) inb(0xa0)) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	       | inb(0x20));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	 * Now for every possible bit set, work through them and call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	 * the appropriate interrupt handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	while (pld) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		i = ffz(~pld);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		pld &= pld - 1; /* clear least bit set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		if (i < 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 			isa_device_interrupt(vector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 			handle_irq(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) mikasa_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	long i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	if (alpha_using_srm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		alpha_mv.device_interrupt = srm_device_interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	mikasa_update_irq_hw(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	for (i = 16; i < 32; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		irq_set_chip_and_handler(i, &mikasa_irq_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 					 handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		irq_set_status_flags(i, IRQ_LEVEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	init_i8259a_irqs();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	common_init_isa_dma();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)  * PCI Fixup configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)  * Summary @ 0x536:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)  * Bit      Meaning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)  * 0        Interrupt Line A from slot 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)  * 1        Interrupt Line B from slot 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)  * 2        Interrupt Line C from slot 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)  * 3        Interrupt Line D from slot 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)  * 4        Interrupt Line A from slot 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)  * 5        Interrupt line B from slot 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)  * 6        Interrupt Line C from slot 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)  * 7        Interrupt Line D from slot 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)  * 8        Interrupt Line A from slot 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)  * 9        Interrupt Line B from slot 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)  *10        Interrupt Line C from slot 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)  *11        Interrupt Line D from slot 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)  *12        NCR 810 SCSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)  *13        Power Supply Fail
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)  *14        Temperature Warn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)  *15        Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)  * The device to slot mapping looks like:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)  * Slot     Device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)  *  6       NCR SCSI controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)  *  7       Intel PCI-EISA bridge chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)  * 11       PCI on board slot 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)  * 12       PCI on board slot 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)  * 13       PCI on board slot 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)  *   
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)  * This two layered interrupt approach means that we allocate IRQ 16 and 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)  * above for PCI interrupts.  The IRQ relates to which bit the interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)  * comes in on.  This makes interrupt processing much easier.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) mikasa_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	static char irq_tab[8][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		/*INT    INTA   INTB   INTC   INTD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		{16+12, 16+12, 16+12, 16+12, 16+12},	/* IdSel 17,  SCSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		{   -1,    -1,    -1,    -1,    -1},	/* IdSel 18,  PCEB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		{   -1,    -1,    -1,    -1,    -1},	/* IdSel 19,  ???? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		{   -1,    -1,    -1,    -1,    -1},	/* IdSel 20,  ???? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		{   -1,    -1,    -1,    -1,    -1},	/* IdSel 21,  ???? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		{ 16+0,  16+0,  16+1,  16+2,  16+3},	/* IdSel 22,  slot 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		{ 16+4,  16+4,  16+5,  16+6,  16+7},	/* IdSel 23,  slot 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		{ 16+8,  16+8,  16+9, 16+10, 16+11},	/* IdSel 24,  slot 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	const long min_idsel = 6, max_idsel = 13, irqs_per_slot = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	return COMMON_TABLE_LOOKUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #if defined(CONFIG_ALPHA_GENERIC) || !defined(CONFIG_ALPHA_PRIMO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) mikasa_apecs_machine_check(unsigned long vector, unsigned long la_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define MCHK_NO_DEVSEL 0x205U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define MCHK_NO_TABT 0x204U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	struct el_common *mchk_header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	unsigned int code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	mchk_header = (struct el_common *)la_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	/* Clear the error before any reporting.  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	mb(); /* magic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	draina();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	apecs_pci_clr_err();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	wrmces(0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	code = mchk_header->code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	process_mcheck_info(vector, la_ptr, "MIKASA APECS",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 			    (mcheck_expected(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 			     && (code == MCHK_NO_DEVSEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 			         || code == MCHK_NO_TABT)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)  * The System Vector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #if defined(CONFIG_ALPHA_GENERIC) || !defined(CONFIG_ALPHA_PRIMO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct alpha_machine_vector mikasa_mv __initmv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	.vector_name		= "Mikasa",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	DO_EV4_MMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	DO_DEFAULT_RTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	DO_APECS_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	.machine_check		= mikasa_apecs_machine_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	.max_isa_dma_address	= ALPHA_MAX_ISA_DMA_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	.min_io_address		= DEFAULT_IO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	.min_mem_address	= APECS_AND_LCA_DEFAULT_MEM_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	.nr_irqs		= 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	.device_interrupt	= mikasa_device_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	.init_arch		= apecs_init_arch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	.init_irq		= mikasa_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	.init_rtc		= common_init_rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	.init_pci		= common_init_pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	.pci_map_irq		= mikasa_map_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	.pci_swizzle		= common_swizzle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ALIAS_MV(mikasa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_PRIMO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct alpha_machine_vector mikasa_primo_mv __initmv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	.vector_name		= "Mikasa-Primo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	DO_EV5_MMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	DO_DEFAULT_RTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	DO_CIA_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	.machine_check		= cia_machine_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	.max_isa_dma_address	= ALPHA_MAX_ISA_DMA_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	.min_io_address		= DEFAULT_IO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	.min_mem_address	= CIA_DEFAULT_MEM_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	.nr_irqs		= 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	.device_interrupt	= mikasa_device_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	.init_arch		= cia_init_arch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	.init_irq		= mikasa_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	.init_rtc		= common_init_rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	.init_pci		= cia_init_pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	.kill_arch		= cia_kill_arch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	.pci_map_irq		= mikasa_map_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	.pci_swizzle		= common_swizzle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) ALIAS_MV(mikasa_primo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #endif