^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/alpha/kernel/sys_miata.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1995 David A Rusling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 1996 Jay A Estabrook
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 1998, 1999, 2000 Richard Henderson
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Code supporting the MIATA (EV56+PYXIS).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/mmu_context.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/core_cia.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/tlbflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "proto.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "irq_impl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "pci_impl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "machvec_impl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) miata_srm_device_interrupt(unsigned long vector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) irq = (vector - 0x800) >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * I really hate to do this, but the MIATA SRM console ignores the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * low 8 bits in the interrupt summary register, and reports the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * vector 0x80 *lower* than I expected from the bit numbering in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * the documentation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * This was done because the low 8 summary bits really aren't used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * for reporting any interrupts (the PCI-ISA bridge, bit 7, isn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * used for this purpose, as PIC interrupts are delivered as the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * vectors 0x800-0x8f0).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * But I really don't want to change the fixup code for allocation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * of IRQs, nor the alpha_irq_mask maintenance stuff, both of which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * look nice and clean now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * So, here's this grotty hack... :-(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) if (irq >= 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) irq = irq + 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) handle_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) miata_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if (alpha_using_srm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) alpha_mv.device_interrupt = miata_srm_device_interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* These break on MiataGL so we'll try not to do it at all. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) *(vulp)PYXIS_INT_HILO = 0x000000B2UL; mb(); /* ISA/NMI HI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) *(vulp)PYXIS_RT_COUNT = 0UL; mb(); /* clear count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) init_i8259a_irqs();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Not interested in the bogus interrupts (3,10), Fan Fault (0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) NMI (1), or EIDE (9).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) We also disable the risers (4,5), since we don't know how to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) route the interrupts behind the bridge. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) init_pyxis_irqs(0x63b0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) common_init_isa_dma();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (request_irq(16 + 2, no_action, 0, "halt-switch", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) pr_err("Failed to register halt-switch interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (request_irq(16 + 6, no_action, 0, "timer-cascade", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) pr_err("Failed to register timer-cascade interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * PCI Fixup configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * Summary @ PYXIS_INT_REQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * Bit Meaning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * 0 Fan Fault
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * 1 NMI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * 2 Halt/Reset switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * 3 none
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * 4 CID0 (Riser ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * 5 CID1 (Riser ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * 6 Interval timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * 7 PCI-ISA Bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * 8 Ethernet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * 9 EIDE (deprecated, ISA 14/15 used)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) *10 none
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) *11 USB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) *12 Interrupt Line A from slot 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) *13 Interrupt Line B from slot 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) *14 Interrupt Line C from slot 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) *15 Interrupt Line D from slot 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) *16 Interrupt Line A from slot 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) *17 Interrupt line B from slot 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) *18 Interrupt Line C from slot 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) *19 Interrupt Line D from slot 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) *20 Interrupt Line A from slot 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) *21 Interrupt Line B from slot 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) *22 Interrupt Line C from slot 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) *23 Interrupt Line D from slot 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) *24 Interrupt Line A from slot 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) *25 Interrupt Line B from slot 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) *26 Interrupt Line C from slot 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) *27 Interrupt Line D from slot 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) *27 Interrupt Line A from slot 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) *29 Interrupt Line B from slot 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) *30 Interrupt Line C from slot 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) *31 Interrupt Line D from slot 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * The device to slot mapping looks like:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * Slot Device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * 3 DC21142 Ethernet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * 4 EIDE CMD646
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * 5 none
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * 6 USB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * 7 PCI-ISA bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * 8 PCI-PCI Bridge (SBU Riser)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * 9 none
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * 10 none
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * 11 PCI on board slot 4 (SBU Riser)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * 12 PCI on board slot 5 (SBU Riser)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * These are behind the bridge, so I'm not sure what to do...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * 13 PCI on board slot 1 (SBU Riser)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * 14 PCI on board slot 2 (SBU Riser)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * 15 PCI on board slot 3 (SBU Riser)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * This two layered interrupt approach means that we allocate IRQ 16 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * above for PCI interrupts. The IRQ relates to which bit the interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * comes in on. This makes interrupt processing much easier.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) miata_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static char irq_tab[18][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /*INT INTA INTB INTC INTD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {16+ 8, 16+ 8, 16+ 8, 16+ 8, 16+ 8}, /* IdSel 14, DC21142 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) { -1, -1, -1, -1, -1}, /* IdSel 15, EIDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) { -1, -1, -1, -1, -1}, /* IdSel 16, none */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) { -1, -1, -1, -1, -1}, /* IdSel 17, none */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) { -1, -1, -1, -1, -1}, /* IdSel 18, PCI-ISA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) { -1, -1, -1, -1, -1}, /* IdSel 19, PCI-PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) { -1, -1, -1, -1, -1}, /* IdSel 20, none */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) { -1, -1, -1, -1, -1}, /* IdSel 21, none */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {16+12, 16+12, 16+13, 16+14, 16+15}, /* IdSel 22, slot 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {16+16, 16+16, 16+17, 16+18, 16+19}, /* IdSel 23, slot 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* the next 7 are actually on PCI bus 1, across the bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {16+11, 16+11, 16+11, 16+11, 16+11}, /* IdSel 24, QLISP/GL*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) { -1, -1, -1, -1, -1}, /* IdSel 25, none */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) { -1, -1, -1, -1, -1}, /* IdSel 26, none */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) { -1, -1, -1, -1, -1}, /* IdSel 27, none */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {16+20, 16+20, 16+21, 16+22, 16+23}, /* IdSel 28, slot 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {16+24, 16+24, 16+25, 16+26, 16+27}, /* IdSel 29, slot 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {16+28, 16+28, 16+29, 16+30, 16+31}, /* IdSel 30, slot 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* This bridge is on the main bus of the later orig MIATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) { -1, -1, -1, -1, -1}, /* IdSel 31, PCI-PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) const long min_idsel = 3, max_idsel = 20, irqs_per_slot = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* the USB function of the 82c693 has it's interrupt connected to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) the 2nd 8259 controller. So we have to check for it first. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if((slot == 7) && (PCI_FUNC(dev->devfn) == 3)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u8 irq=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct pci_dev *pdev = pci_get_slot(dev->bus, dev->devfn & ~7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if(pdev == NULL || pci_read_config_byte(pdev, 0x40,&irq) != PCIBIOS_SUCCESSFUL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) pci_dev_put(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) pci_dev_put(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return COMMON_TABLE_LOOKUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static u8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) miata_swizzle(struct pci_dev *dev, u8 *pinp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) int slot, pin = *pinp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (dev->bus->number == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) slot = PCI_SLOT(dev->devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* Check for the built-in bridge. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) else if ((PCI_SLOT(dev->bus->self->devfn) == 8) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) (PCI_SLOT(dev->bus->self->devfn) == 20)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) slot = PCI_SLOT(dev->devfn) + 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* Must be a card-based bridge. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if ((PCI_SLOT(dev->bus->self->devfn) == 8) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) (PCI_SLOT(dev->bus->self->devfn) == 20)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) slot = PCI_SLOT(dev->devfn) + 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) pin = pci_swizzle_interrupt_pin(dev, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* Move up the chain of bridges. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) dev = dev->bus->self;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* Slot of the next bridge. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) slot = PCI_SLOT(dev->devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) } while (dev->bus->self);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) *pinp = pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) miata_init_pci(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) cia_init_pci();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) SMC669_Init(0); /* it might be a GL (fails harmlessly if not) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) es1888_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) miata_kill_arch(int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) cia_kill_arch(mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #ifndef ALPHA_RESTORE_SRM_SETUP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) switch(mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) case LINUX_REBOOT_CMD_RESTART:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* Who said DEC engineers have no sense of humor? ;-) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (alpha_using_srm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) *(vuip) PYXIS_RESET = 0x0000dead;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) case LINUX_REBOOT_CMD_HALT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) case LINUX_REBOOT_CMD_POWER_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) halt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * The System Vector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct alpha_machine_vector miata_mv __initmv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .vector_name = "Miata",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) DO_EV5_MMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) DO_DEFAULT_RTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) DO_PYXIS_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .machine_check = cia_machine_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .min_io_address = DEFAULT_IO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .min_mem_address = DEFAULT_MEM_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .pci_dac_offset = PYXIS_DAC_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .nr_irqs = 48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .device_interrupt = pyxis_device_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .init_arch = pyxis_init_arch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .init_irq = miata_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .init_rtc = common_init_rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .init_pci = miata_init_pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .kill_arch = miata_kill_arch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .pci_map_irq = miata_map_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .pci_swizzle = miata_swizzle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) ALIAS_MV(miata)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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