^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/alpha/kernel/sys_marvel.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Marvel / IO7 support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/mmu_context.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/core_marvel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/hwrpb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/tlbflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/vga.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "proto.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "err_impl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "irq_impl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "pci_impl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "machvec_impl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #if NR_IRQS < MARVEL_NR_IRQS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) # error NR_IRQS < MARVEL_NR_IRQS !!!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * Interrupt handling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) io7_device_interrupt(unsigned long vector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) unsigned int pid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * Vector is 0x800 + (interrupt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * where (interrupt) is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * ...16|15 14|13 4|3 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * -----+-----+--------+---
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * PE | 0 | irq | 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * where (irq) is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * 0x0800 - 0x0ff0 - 0x0800 + (LSI id << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * 0x1000 - 0x2ff0 - 0x1000 + (MSI_DAT<8:0> << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) pid = vector >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) irq = ((vector & 0xffff) - 0x800) >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) irq += 16; /* offset for legacy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) irq &= MARVEL_IRQ_VEC_IRQ_MASK; /* not too many bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) irq |= pid << MARVEL_IRQ_VEC_PE_SHIFT; /* merge the pid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) handle_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static volatile unsigned long *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) io7_get_irq_ctl(unsigned int irq, struct io7 **pio7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) volatile unsigned long *ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) unsigned int pid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct io7 *io7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) pid = irq >> MARVEL_IRQ_VEC_PE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (!(io7 = marvel_find_io7(pid))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) printk(KERN_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) "%s for nonexistent io7 -- vec %x, pid %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) __func__, irq, pid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) irq &= MARVEL_IRQ_VEC_IRQ_MASK; /* isolate the vector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) irq -= 16; /* subtract legacy bias */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (irq >= 0x180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) printk(KERN_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) "%s for invalid irq -- pid %d adjusted irq %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) __func__, pid, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) ctl = &io7->csrs->PO7_LSI_CTL[irq & 0xff].csr; /* assume LSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (irq >= 0x80) /* MSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) ctl = &io7->csrs->PO7_MSI_CTL[((irq - 0x80) >> 5) & 0x0f].csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (pio7) *pio7 = io7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) io7_enable_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) volatile unsigned long *ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) unsigned int irq = d->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct io7 *io7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ctl = io7_get_irq_ctl(irq, &io7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (!ctl || !io7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) printk(KERN_ERR "%s: get_ctl failed for irq %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) __func__, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) raw_spin_lock(&io7->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) *ctl |= 1UL << 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) *ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) raw_spin_unlock(&io7->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) io7_disable_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) volatile unsigned long *ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) unsigned int irq = d->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct io7 *io7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) ctl = io7_get_irq_ctl(irq, &io7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (!ctl || !io7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) printk(KERN_ERR "%s: get_ctl failed for irq %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) __func__, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) raw_spin_lock(&io7->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) *ctl &= ~(1UL << 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) *ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) raw_spin_unlock(&io7->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) marvel_irq_noop(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static struct irq_chip marvel_legacy_irq_type = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .name = "LEGACY",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .irq_mask = marvel_irq_noop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .irq_unmask = marvel_irq_noop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static struct irq_chip io7_lsi_irq_type = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .name = "LSI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .irq_unmask = io7_enable_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .irq_mask = io7_disable_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .irq_mask_ack = io7_disable_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static struct irq_chip io7_msi_irq_type = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .name = "MSI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .irq_unmask = io7_enable_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .irq_mask = io7_disable_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .irq_ack = marvel_irq_noop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) io7_redirect_irq(struct io7 *io7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) volatile unsigned long *csr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) unsigned int where)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) val = *csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) val &= ~(0x1ffUL << 24); /* clear the target pid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) val |= ((unsigned long)where << 24); /* set the new target pid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) *csr = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) *csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) io7_redirect_one_lsi(struct io7 *io7, unsigned int which, unsigned int where)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * LSI_CTL has target PID @ 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) val = io7->csrs->PO7_LSI_CTL[which].csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) val &= ~(0x1ffUL << 14); /* clear the target pid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) val |= ((unsigned long)where << 14); /* set the new target pid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) io7->csrs->PO7_LSI_CTL[which].csr = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) io7->csrs->PO7_LSI_CTL[which].csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) io7_redirect_one_msi(struct io7 *io7, unsigned int which, unsigned int where)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * MSI_CTL has target PID @ 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) val = io7->csrs->PO7_MSI_CTL[which].csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) val &= ~(0x1ffUL << 14); /* clear the target pid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) val |= ((unsigned long)where << 14); /* set the new target pid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) io7->csrs->PO7_MSI_CTL[which].csr = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) io7->csrs->PO7_MSI_CTL[which].csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) init_one_io7_lsi(struct io7 *io7, unsigned int which, unsigned int where)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * LSI_CTL has target PID @ 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) io7->csrs->PO7_LSI_CTL[which].csr = ((unsigned long)where << 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) io7->csrs->PO7_LSI_CTL[which].csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) init_one_io7_msi(struct io7 *io7, unsigned int which, unsigned int where)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * MSI_CTL has target PID @ 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) io7->csrs->PO7_MSI_CTL[which].csr = ((unsigned long)where << 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) io7->csrs->PO7_MSI_CTL[which].csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) init_io7_irqs(struct io7 *io7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct irq_chip *lsi_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct irq_chip *msi_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) long base = (io7->pe << MARVEL_IRQ_VEC_PE_SHIFT) + 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) long i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) printk("Initializing interrupts for IO7 at PE %u - base %lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) io7->pe, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * Where should interrupts from this IO7 go?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * They really should be sent to the local CPU to avoid having to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * traverse the mesh, but if it's not an SMP kernel, they have to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * go to the boot CPU. Send them all to the boot CPU for now,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * as each secondary starts, it can redirect it's local device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) printk(" Interrupts reported to CPU at PE %u\n", boot_cpuid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) raw_spin_lock(&io7->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* set up the error irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) io7_redirect_irq(io7, &io7->csrs->HLT_CTL.csr, boot_cpuid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) io7_redirect_irq(io7, &io7->csrs->HPI_CTL.csr, boot_cpuid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) io7_redirect_irq(io7, &io7->csrs->CRD_CTL.csr, boot_cpuid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) io7_redirect_irq(io7, &io7->csrs->STV_CTL.csr, boot_cpuid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) io7_redirect_irq(io7, &io7->csrs->HEI_CTL.csr, boot_cpuid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* Set up the lsi irqs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) for (i = 0; i < 128; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) irq_set_chip_and_handler(base + i, lsi_ops, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) irq_set_status_flags(i, IRQ_LEVEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* Disable the implemented irqs in hardware. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) for (i = 0; i < 0x60; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) init_one_io7_lsi(io7, i, boot_cpuid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) init_one_io7_lsi(io7, 0x74, boot_cpuid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) init_one_io7_lsi(io7, 0x75, boot_cpuid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* Set up the msi irqs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) for (i = 128; i < (128 + 512); ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) irq_set_chip_and_handler(base + i, msi_ops, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) irq_set_status_flags(i, IRQ_LEVEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) for (i = 0; i < 16; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) init_one_io7_msi(io7, i, boot_cpuid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) raw_spin_unlock(&io7->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) marvel_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct io7 *io7 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* Reserve the legacy irqs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) for (i = 0; i < 16; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) irq_set_chip_and_handler(i, &marvel_legacy_irq_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* Init the io7 irqs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) for (io7 = NULL; (io7 = marvel_next_io7(io7)) != NULL; )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) init_io7_irqs(io7, &io7_lsi_irq_type, &io7_msi_irq_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) marvel_map_irq(const struct pci_dev *cdev, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct pci_dev *dev = (struct pci_dev *)cdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct pci_controller *hose = dev->sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct io7_port *io7_port = hose->sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct io7 *io7 = io7_port->io7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) int msi_loc, msi_data_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) u16 msg_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) u16 msg_dat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) u8 intline;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &intline);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) irq = intline;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) msi_loc = dev->msi_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) msg_ctl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (msi_loc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) pci_read_config_word(dev, msi_loc + PCI_MSI_FLAGS, &msg_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (msg_ctl & PCI_MSI_FLAGS_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) msi_data_off = PCI_MSI_DATA_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (msg_ctl & PCI_MSI_FLAGS_64BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) msi_data_off = PCI_MSI_DATA_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) pci_read_config_word(dev, msi_loc + msi_data_off, &msg_dat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) irq = msg_dat & 0x1ff; /* we use msg_data<8:0> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) irq += 0x80; /* offset for lsi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #if 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) printk("PCI:%d:%d:%d (hose %d) is using MSI\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) dev->bus->number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) PCI_SLOT(dev->devfn),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) PCI_FUNC(dev->devfn),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) hose->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) printk(" %d message(s) from 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 1 << ((msg_ctl & PCI_MSI_FLAGS_QSIZE) >> 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) msg_dat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) printk(" reporting on %d IRQ(s) from %d (0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 1 << ((msg_ctl & PCI_MSI_FLAGS_QSIZE) >> 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) (irq + 16) | (io7->pe << MARVEL_IRQ_VEC_PE_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) (irq + 16) | (io7->pe << MARVEL_IRQ_VEC_PE_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) pci_write_config_word(dev, msi_loc + PCI_MSI_FLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) msg_ctl & ~PCI_MSI_FLAGS_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &intline);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) irq = intline;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) printk(" forcing LSI interrupt on irq %d [0x%x]\n", irq, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) irq += 16; /* offset for legacy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) irq |= io7->pe << MARVEL_IRQ_VEC_PE_SHIFT; /* merge the pid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) marvel_init_pci(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct io7 *io7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) marvel_register_error_handlers();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* Indicate that we trust the console to configure things properly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) pci_set_flags(PCI_PROBE_ONLY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) common_init_pci();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) locate_and_init_vga(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* Clear any io7 errors. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) for (io7 = NULL; (io7 = marvel_next_io7(io7)) != NULL; )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) io7_clear_errors(io7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) marvel_init_rtc(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) init_rtc_irq(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) marvel_smp_callin(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) int cpuid = hard_smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct io7 *io7 = marvel_find_io7(cpuid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (!io7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * There is a local IO7 - redirect all of its interrupts here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) printk("Redirecting IO7 interrupts to local CPU at PE %u\n", cpuid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* Redirect the error IRQS here. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) io7_redirect_irq(io7, &io7->csrs->HLT_CTL.csr, cpuid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) io7_redirect_irq(io7, &io7->csrs->HPI_CTL.csr, cpuid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) io7_redirect_irq(io7, &io7->csrs->CRD_CTL.csr, cpuid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) io7_redirect_irq(io7, &io7->csrs->STV_CTL.csr, cpuid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) io7_redirect_irq(io7, &io7->csrs->HEI_CTL.csr, cpuid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* Redirect the implemented LSIs here. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) for (i = 0; i < 0x60; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) io7_redirect_one_lsi(io7, i, cpuid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) io7_redirect_one_lsi(io7, 0x74, cpuid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) io7_redirect_one_lsi(io7, 0x75, cpuid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* Redirect the MSIs here. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) for (i = 0; i < 16; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) io7_redirect_one_msi(io7, i, cpuid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * System Vectors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) struct alpha_machine_vector marvel_ev7_mv __initmv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .vector_name = "MARVEL/EV7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) DO_EV7_MMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .rtc_port = 0x70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .rtc_boot_cpu_only = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) DO_MARVEL_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .machine_check = marvel_machine_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .min_io_address = DEFAULT_IO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .min_mem_address = DEFAULT_MEM_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .pci_dac_offset = IO7_DAC_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .nr_irqs = MARVEL_NR_IRQS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .device_interrupt = io7_device_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .agp_info = marvel_agp_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .smp_callin = marvel_smp_callin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .init_arch = marvel_init_arch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .init_irq = marvel_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .init_rtc = marvel_init_rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .init_pci = marvel_init_pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .kill_arch = marvel_kill_arch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .pci_map_irq = marvel_map_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .pci_swizzle = common_swizzle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .pa_to_nid = marvel_pa_to_nid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .cpuid_to_nid = marvel_cpuid_to_nid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .node_mem_start = marvel_node_mem_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .node_mem_size = marvel_node_mem_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) ALIAS_MV(marvel_ev7)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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