^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/alpha/kernel/sys_eb64p.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1995 David A Rusling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 1996 Jay A Estabrook
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 1998, 1999 Richard Henderson
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Code supporting the EB64+ and EB66.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/mmu_context.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/core_apecs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/core_lca.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/hwrpb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/tlbflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "proto.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "irq_impl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include "pci_impl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include "machvec_impl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* Note mask bit is true for DISABLED irqs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static unsigned int cached_irq_mask = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) eb64p_update_irq_hw(unsigned int irq, unsigned long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) outb(mask >> (irq >= 24 ? 24 : 16), (irq >= 24 ? 0x27 : 0x26));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) eb64p_enable_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) eb64p_update_irq_hw(d->irq, cached_irq_mask &= ~(1 << d->irq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) eb64p_disable_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) eb64p_update_irq_hw(d->irq, cached_irq_mask |= 1 << d->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static struct irq_chip eb64p_irq_type = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .name = "EB64P",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .irq_unmask = eb64p_enable_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .irq_mask = eb64p_disable_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .irq_mask_ack = eb64p_disable_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) eb64p_device_interrupt(unsigned long vector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) unsigned long pld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* Read the interrupt summary registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) pld = inb(0x26) | (inb(0x27) << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * Now, for every possible bit set, work through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * them and call the appropriate interrupt handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) while (pld) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) i = ffz(~pld);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) pld &= pld - 1; /* clear least bit set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (i == 5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) isa_device_interrupt(vector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) handle_irq(16 + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) eb64p_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) long i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_CABRIOLET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * CABRIO SRM may not set variation correctly, so here we test
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * the high word of the interrupt summary register for the RAZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * bits, and hope that a true EB64+ would read all ones...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (inw(0x806) != 0xffff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) extern struct alpha_machine_vector cabriolet_mv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) printk("Detected Cabriolet: correcting HWRPB.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) hwrpb->sys_variation |= 2L << 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) hwrpb_update_checksum(hwrpb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) alpha_mv = cabriolet_mv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) alpha_mv.init_irq();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #endif /* GENERIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) outb(0xff, 0x26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) outb(0xff, 0x27);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) init_i8259a_irqs();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) for (i = 16; i < 32; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) irq_set_chip_and_handler(i, &eb64p_irq_type, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) irq_set_status_flags(i, IRQ_LEVEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) common_init_isa_dma();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (request_irq(16 + 5, no_action, 0, "isa-cascade", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) pr_err("Failed to register isa-cascade interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * PCI Fixup configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * There are two 8 bit external summary registers as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * Summary @ 0x26:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * Bit Meaning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * 0 Interrupt Line A from slot 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * 1 Interrupt Line A from slot 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * 2 Interrupt Line B from slot 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * 3 Interrupt Line B from slot 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * 4 Interrupt Line C from slot 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * 5 Interrupt line from the two ISA PICs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * 6 Tulip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * 7 NCR SCSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * Summary @ 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * Bit Meaning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * 0 Interrupt Line C from slot 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * 1 Interrupt Line D from slot 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * 2 Interrupt Line D from slot 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * 3 RAZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * 4 RAZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * 5 RAZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * 6 RAZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * 7 RAZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * The device to slot mapping looks like:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * Slot Device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * 5 NCR SCSI controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * 6 PCI on board slot 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * 7 PCI on board slot 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * 8 Intel SIO PCI-ISA bridge chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * 9 Tulip - DECchip 21040 Ethernet controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * This two layered interrupt approach means that we allocate IRQ 16 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * above for PCI interrupts. The IRQ relates to which bit the interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * comes in on. This makes interrupt processing much easier.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) eb64p_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static char irq_tab[5][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /*INT INTA INTB INTC INTD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {16+7, 16+7, 16+7, 16+7, 16+7}, /* IdSel 5, slot ?, ?? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {16+0, 16+0, 16+2, 16+4, 16+9}, /* IdSel 6, slot ?, ?? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {16+1, 16+1, 16+3, 16+8, 16+10}, /* IdSel 7, slot ?, ?? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) { -1, -1, -1, -1, -1}, /* IdSel 8, SIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {16+6, 16+6, 16+6, 16+6, 16+6}, /* IdSel 9, TULIP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) const long min_idsel = 5, max_idsel = 9, irqs_per_slot = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return COMMON_TABLE_LOOKUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * The System Vector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_EB64P)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct alpha_machine_vector eb64p_mv __initmv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .vector_name = "EB64+",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) DO_EV4_MMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) DO_DEFAULT_RTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) DO_APECS_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .machine_check = apecs_machine_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .min_io_address = DEFAULT_IO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .nr_irqs = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .device_interrupt = eb64p_device_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .init_arch = apecs_init_arch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .init_irq = eb64p_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .init_rtc = common_init_rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .init_pci = common_init_pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .kill_arch = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .pci_map_irq = eb64p_map_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .pci_swizzle = common_swizzle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) ALIAS_MV(eb64p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_EB66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct alpha_machine_vector eb66_mv __initmv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .vector_name = "EB66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) DO_EV4_MMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) DO_DEFAULT_RTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) DO_LCA_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .machine_check = lca_machine_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .min_io_address = DEFAULT_IO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .nr_irqs = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .device_interrupt = eb64p_device_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .init_arch = lca_init_arch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .init_irq = eb64p_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .init_rtc = common_init_rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .init_pci = common_init_pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .pci_map_irq = eb64p_map_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .pci_swizzle = common_swizzle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) ALIAS_MV(eb66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags