^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/alpha/kernel/sys_dp264.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1995 David A Rusling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 1996, 1999 Jay A Estabrook
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 1998, 1999 Richard Henderson
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Modified by Christopher C. Chimelis, 2001 to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * add support for the addition of Shark to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Tsunami family.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Code supporting the DP264 (EV6+TSUNAMI).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/mmu_context.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/core_tsunami.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <asm/hwrpb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <asm/tlbflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include "proto.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include "irq_impl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include "pci_impl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include "machvec_impl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* Note mask bit is true for ENABLED irqs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static unsigned long cached_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* dp264 boards handle at max four CPUs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static unsigned long cpu_irq_affinity[4] = { 0UL, 0UL, 0UL, 0UL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) DEFINE_SPINLOCK(dp264_irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) tsunami_update_irq_hw(unsigned long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) register tsunami_cchip *cchip = TSUNAMI_cchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) unsigned long isa_enable = 1UL << 55;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) register int bcpu = boot_cpuid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) volatile unsigned long *dim0, *dim1, *dim2, *dim3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) unsigned long mask0, mask1, mask2, mask3, dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) mask &= ~isa_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) mask0 = mask & cpu_irq_affinity[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) mask1 = mask & cpu_irq_affinity[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) mask2 = mask & cpu_irq_affinity[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) mask3 = mask & cpu_irq_affinity[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (bcpu == 0) mask0 |= isa_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) else if (bcpu == 1) mask1 |= isa_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) else if (bcpu == 2) mask2 |= isa_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) else mask3 |= isa_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) dim0 = &cchip->dim0.csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) dim1 = &cchip->dim1.csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) dim2 = &cchip->dim2.csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) dim3 = &cchip->dim3.csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (!cpu_possible(0)) dim0 = &dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (!cpu_possible(1)) dim1 = &dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (!cpu_possible(2)) dim2 = &dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (!cpu_possible(3)) dim3 = &dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) *dim0 = mask0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) *dim1 = mask1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) *dim2 = mask2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) *dim3 = mask3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) *dim0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) *dim1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) *dim2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) *dim3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) volatile unsigned long *dimB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (bcpu == 0) dimB = &cchip->dim0.csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) else if (bcpu == 1) dimB = &cchip->dim1.csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) else if (bcpu == 2) dimB = &cchip->dim2.csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) else dimB = &cchip->dim3.csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) *dimB = mask | isa_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) *dimB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) dp264_enable_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) spin_lock(&dp264_irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) cached_irq_mask |= 1UL << d->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) tsunami_update_irq_hw(cached_irq_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) spin_unlock(&dp264_irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) dp264_disable_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) spin_lock(&dp264_irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) cached_irq_mask &= ~(1UL << d->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) tsunami_update_irq_hw(cached_irq_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) spin_unlock(&dp264_irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) clipper_enable_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) spin_lock(&dp264_irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) cached_irq_mask |= 1UL << (d->irq - 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) tsunami_update_irq_hw(cached_irq_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) spin_unlock(&dp264_irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) clipper_disable_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) spin_lock(&dp264_irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) cached_irq_mask &= ~(1UL << (d->irq - 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) tsunami_update_irq_hw(cached_irq_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) spin_unlock(&dp264_irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) cpu_set_irq_affinity(unsigned int irq, cpumask_t affinity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) for (cpu = 0; cpu < 4; cpu++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) unsigned long aff = cpu_irq_affinity[cpu];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (cpumask_test_cpu(cpu, &affinity))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) aff |= 1UL << irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) aff &= ~(1UL << irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) cpu_irq_affinity[cpu] = aff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) dp264_set_affinity(struct irq_data *d, const struct cpumask *affinity,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) bool force)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) spin_lock(&dp264_irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) cpu_set_irq_affinity(d->irq, *affinity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) tsunami_update_irq_hw(cached_irq_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) spin_unlock(&dp264_irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) clipper_set_affinity(struct irq_data *d, const struct cpumask *affinity,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) bool force)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) spin_lock(&dp264_irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) cpu_set_irq_affinity(d->irq - 16, *affinity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) tsunami_update_irq_hw(cached_irq_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) spin_unlock(&dp264_irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static struct irq_chip dp264_irq_type = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .name = "DP264",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .irq_unmask = dp264_enable_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .irq_mask = dp264_disable_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .irq_mask_ack = dp264_disable_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .irq_set_affinity = dp264_set_affinity,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static struct irq_chip clipper_irq_type = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .name = "CLIPPER",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .irq_unmask = clipper_enable_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .irq_mask = clipper_disable_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .irq_mask_ack = clipper_disable_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .irq_set_affinity = clipper_set_affinity,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) dp264_device_interrupt(unsigned long vector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) unsigned long pld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* Read the interrupt summary register of TSUNAMI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) pld = TSUNAMI_cchip->dir0.csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * Now for every possible bit set, work through them and call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * the appropriate interrupt handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) while (pld) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) i = ffz(~pld);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) pld &= pld - 1; /* clear least bit set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (i == 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) isa_device_interrupt(vector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) handle_irq(16 + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) dp264_srm_device_interrupt(unsigned long vector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) irq = (vector - 0x800) >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * The SRM console reports PCI interrupts with a vector calculated by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * 0x900 + (0x10 * DRIR-bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * So bit 16 shows up as IRQ 32, etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * On DP264/BRICK/MONET, we adjust it down by 16 because at least
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * that many of the low order bits of the DRIR are not used, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * so we don't count them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (irq >= 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) irq -= 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) handle_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) clipper_srm_device_interrupt(unsigned long vector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) irq = (vector - 0x800) >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * The SRM console reports PCI interrupts with a vector calculated by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * 0x900 + (0x10 * DRIR-bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * So bit 16 shows up as IRQ 32, etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * CLIPPER uses bits 8-47 for PCI interrupts, so we do not need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * to scale down the vector reported, we just use it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * Eg IRQ 24 is DRIR bit 8, etc, etc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) handle_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) init_tsunami_irqs(struct irq_chip * ops, int imin, int imax)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) long i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) for (i = imin; i <= imax; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) irq_set_chip_and_handler(i, ops, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) irq_set_status_flags(i, IRQ_LEVEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) dp264_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) outb(0, DMA1_RESET_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) outb(0, DMA2_RESET_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) outb(DMA_MODE_CASCADE, DMA2_MODE_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) outb(0, DMA2_MASK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (alpha_using_srm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) alpha_mv.device_interrupt = dp264_srm_device_interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) tsunami_update_irq_hw(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) init_i8259a_irqs();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) init_tsunami_irqs(&dp264_irq_type, 16, 47);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) clipper_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) outb(0, DMA1_RESET_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) outb(0, DMA2_RESET_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) outb(DMA_MODE_CASCADE, DMA2_MODE_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) outb(0, DMA2_MASK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (alpha_using_srm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) alpha_mv.device_interrupt = clipper_srm_device_interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) tsunami_update_irq_hw(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) init_i8259a_irqs();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) init_tsunami_irqs(&clipper_irq_type, 24, 63);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * PCI Fixup configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * Summary @ TSUNAMI_CSR_DIM0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * Bit Meaning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * 0-17 Unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) *18 Interrupt SCSI B (Adaptec 7895 builtin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) *19 Interrupt SCSI A (Adaptec 7895 builtin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) *20 Interrupt Line D from slot 2 PCI0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) *21 Interrupt Line C from slot 2 PCI0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) *22 Interrupt Line B from slot 2 PCI0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) *23 Interrupt Line A from slot 2 PCI0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) *24 Interrupt Line D from slot 1 PCI0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) *25 Interrupt Line C from slot 1 PCI0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) *26 Interrupt Line B from slot 1 PCI0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) *27 Interrupt Line A from slot 1 PCI0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) *28 Interrupt Line D from slot 0 PCI0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) *29 Interrupt Line C from slot 0 PCI0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) *30 Interrupt Line B from slot 0 PCI0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) *31 Interrupt Line A from slot 0 PCI0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) *32 Interrupt Line D from slot 3 PCI1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) *33 Interrupt Line C from slot 3 PCI1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) *34 Interrupt Line B from slot 3 PCI1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) *35 Interrupt Line A from slot 3 PCI1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) *36 Interrupt Line D from slot 2 PCI1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) *37 Interrupt Line C from slot 2 PCI1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) *38 Interrupt Line B from slot 2 PCI1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) *39 Interrupt Line A from slot 2 PCI1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) *40 Interrupt Line D from slot 1 PCI1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) *41 Interrupt Line C from slot 1 PCI1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) *42 Interrupt Line B from slot 1 PCI1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) *43 Interrupt Line A from slot 1 PCI1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) *44 Interrupt Line D from slot 0 PCI1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) *45 Interrupt Line C from slot 0 PCI1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) *46 Interrupt Line B from slot 0 PCI1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) *47 Interrupt Line A from slot 0 PCI1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) *48-52 Unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) *53 PCI0 NMI (from Cypress)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) *54 PCI0 SMI INT (from Cypress)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) *55 PCI0 ISA Interrupt (from Cypress)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) *56-60 Unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) *61 PCI1 Bus Error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) *62 PCI0 Bus Error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) *63 Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * IdSel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * 5 Cypress Bridge I/O
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * 6 SCSI Adaptec builtin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * 7 64 bit PCI option slot 0 (all busses)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * 8 64 bit PCI option slot 1 (all busses)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * 9 64 bit PCI option slot 2 (all busses)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * 10 64 bit PCI option slot 3 (not bus 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) isa_irq_fixup(const struct pci_dev *dev, int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) u8 irq8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (irq > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* This interrupt is routed via ISA bridge, so we'll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) just have to trust whatever value the console might
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) have assigned. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return irq8 & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) dp264_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static char irq_tab[6][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /*INT INTA INTB INTC INTD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) { -1, -1, -1, -1, -1}, /* IdSel 5 ISA Bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) { 16+ 3, 16+ 3, 16+ 2, 16+ 2, 16+ 2}, /* IdSel 6 SCSI builtin*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) { 16+15, 16+15, 16+14, 16+13, 16+12}, /* IdSel 7 slot 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) { 16+11, 16+11, 16+10, 16+ 9, 16+ 8}, /* IdSel 8 slot 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) { 16+ 7, 16+ 7, 16+ 6, 16+ 5, 16+ 4}, /* IdSel 9 slot 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) { 16+ 3, 16+ 3, 16+ 2, 16+ 1, 16+ 0} /* IdSel 10 slot 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) const long min_idsel = 5, max_idsel = 10, irqs_per_slot = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct pci_controller *hose = dev->sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) int irq = COMMON_TABLE_LOOKUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (irq > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) irq += 16 * hose->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return isa_irq_fixup(dev, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) monet_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static char irq_tab[13][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /*INT INTA INTB INTC INTD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) { 45, 45, 45, 45, 45}, /* IdSel 3 21143 PCI1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) { -1, -1, -1, -1, -1}, /* IdSel 4 unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) { -1, -1, -1, -1, -1}, /* IdSel 5 unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) { 47, 47, 47, 47, 47}, /* IdSel 6 SCSI PCI1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) { -1, -1, -1, -1, -1}, /* IdSel 7 ISA Bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) { -1, -1, -1, -1, -1}, /* IdSel 8 P2P PCI1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #if 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) { 28, 28, 29, 30, 31}, /* IdSel 14 slot 4 PCI2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) { 24, 24, 25, 26, 27}, /* IdSel 15 slot 5 PCI2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) { -1, -1, -1, -1, -1}, /* IdSel 9 unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) { -1, -1, -1, -1, -1}, /* IdSel 10 unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) { 40, 40, 41, 42, 43}, /* IdSel 11 slot 1 PCI0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) { 36, 36, 37, 38, 39}, /* IdSel 12 slot 2 PCI0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) { 32, 32, 33, 34, 35}, /* IdSel 13 slot 3 PCI0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) { 28, 28, 29, 30, 31}, /* IdSel 14 slot 4 PCI2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) { 24, 24, 25, 26, 27} /* IdSel 15 slot 5 PCI2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) const long min_idsel = 3, max_idsel = 15, irqs_per_slot = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return isa_irq_fixup(dev, COMMON_TABLE_LOOKUP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static u8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) monet_swizzle(struct pci_dev *dev, u8 *pinp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct pci_controller *hose = dev->sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) int slot, pin = *pinp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (!dev->bus->parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) slot = PCI_SLOT(dev->devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /* Check for the built-in bridge on hose 1. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) else if (hose->index == 1 && PCI_SLOT(dev->bus->self->devfn) == 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) slot = PCI_SLOT(dev->devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /* Must be a card-based bridge. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /* Check for built-in bridge on hose 1. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (hose->index == 1 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) PCI_SLOT(dev->bus->self->devfn) == 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) slot = PCI_SLOT(dev->devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) pin = pci_swizzle_interrupt_pin(dev, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /* Move up the chain of bridges. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) dev = dev->bus->self;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* Slot of the next bridge. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) slot = PCI_SLOT(dev->devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) } while (dev->bus->self);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) *pinp = pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) webbrick_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static char irq_tab[13][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /*INT INTA INTB INTC INTD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) { -1, -1, -1, -1, -1}, /* IdSel 7 ISA Bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) { -1, -1, -1, -1, -1}, /* IdSel 8 unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) { 29, 29, 29, 29, 29}, /* IdSel 9 21143 #1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) { -1, -1, -1, -1, -1}, /* IdSel 10 unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) { 30, 30, 30, 30, 30}, /* IdSel 11 21143 #2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) { -1, -1, -1, -1, -1}, /* IdSel 12 unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) { -1, -1, -1, -1, -1}, /* IdSel 13 unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) { 35, 35, 34, 33, 32}, /* IdSel 14 slot 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) { 39, 39, 38, 37, 36}, /* IdSel 15 slot 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) { 43, 43, 42, 41, 40}, /* IdSel 16 slot 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) { 47, 47, 46, 45, 44}, /* IdSel 17 slot 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) const long min_idsel = 7, max_idsel = 17, irqs_per_slot = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return isa_irq_fixup(dev, COMMON_TABLE_LOOKUP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) clipper_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static char irq_tab[7][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /*INT INTA INTB INTC INTD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) { 16+ 8, 16+ 8, 16+ 9, 16+10, 16+11}, /* IdSel 1 slot 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) { 16+12, 16+12, 16+13, 16+14, 16+15}, /* IdSel 2 slot 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) { 16+16, 16+16, 16+17, 16+18, 16+19}, /* IdSel 3 slot 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) { 16+20, 16+20, 16+21, 16+22, 16+23}, /* IdSel 4 slot 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) { 16+24, 16+24, 16+25, 16+26, 16+27}, /* IdSel 5 slot 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) { 16+28, 16+28, 16+29, 16+30, 16+31}, /* IdSel 6 slot 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) { -1, -1, -1, -1, -1} /* IdSel 7 ISA Bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) const long min_idsel = 1, max_idsel = 7, irqs_per_slot = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) struct pci_controller *hose = dev->sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) int irq = COMMON_TABLE_LOOKUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (irq > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) irq += 16 * hose->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return isa_irq_fixup(dev, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) dp264_init_pci(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) common_init_pci();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) SMC669_Init(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) locate_and_init_vga(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) monet_init_pci(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) common_init_pci();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) SMC669_Init(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) es1888_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) locate_and_init_vga(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) clipper_init_pci(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) common_init_pci();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) locate_and_init_vga(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) webbrick_init_arch(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) tsunami_init_arch();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) /* Tsunami caches 4 PTEs at a time; DS10 has only 1 hose. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) hose_head->sg_isa->align_entry = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) hose_head->sg_pci->align_entry = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * The System Vectors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct alpha_machine_vector dp264_mv __initmv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .vector_name = "DP264",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) DO_EV6_MMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) DO_DEFAULT_RTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) DO_TSUNAMI_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .machine_check = tsunami_machine_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .min_io_address = DEFAULT_IO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .min_mem_address = DEFAULT_MEM_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .pci_dac_offset = TSUNAMI_DAC_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .nr_irqs = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .device_interrupt = dp264_device_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .init_arch = tsunami_init_arch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .init_irq = dp264_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .init_rtc = common_init_rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .init_pci = dp264_init_pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .kill_arch = tsunami_kill_arch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .pci_map_irq = dp264_map_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .pci_swizzle = common_swizzle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) ALIAS_MV(dp264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) struct alpha_machine_vector monet_mv __initmv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .vector_name = "Monet",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) DO_EV6_MMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) DO_DEFAULT_RTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) DO_TSUNAMI_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .machine_check = tsunami_machine_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .min_io_address = DEFAULT_IO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .min_mem_address = DEFAULT_MEM_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .pci_dac_offset = TSUNAMI_DAC_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .nr_irqs = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .device_interrupt = dp264_device_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .init_arch = tsunami_init_arch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .init_irq = dp264_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .init_rtc = common_init_rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .init_pci = monet_init_pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .kill_arch = tsunami_kill_arch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .pci_map_irq = monet_map_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .pci_swizzle = monet_swizzle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) struct alpha_machine_vector webbrick_mv __initmv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .vector_name = "Webbrick",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) DO_EV6_MMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) DO_DEFAULT_RTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) DO_TSUNAMI_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .machine_check = tsunami_machine_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .min_io_address = DEFAULT_IO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .min_mem_address = DEFAULT_MEM_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .pci_dac_offset = TSUNAMI_DAC_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .nr_irqs = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .device_interrupt = dp264_device_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .init_arch = webbrick_init_arch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .init_irq = dp264_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .init_rtc = common_init_rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .init_pci = common_init_pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .kill_arch = tsunami_kill_arch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .pci_map_irq = webbrick_map_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .pci_swizzle = common_swizzle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) struct alpha_machine_vector clipper_mv __initmv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .vector_name = "Clipper",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) DO_EV6_MMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) DO_DEFAULT_RTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) DO_TSUNAMI_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .machine_check = tsunami_machine_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .min_io_address = DEFAULT_IO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .min_mem_address = DEFAULT_MEM_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .pci_dac_offset = TSUNAMI_DAC_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .nr_irqs = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .device_interrupt = dp264_device_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .init_arch = tsunami_init_arch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .init_irq = clipper_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .init_rtc = common_init_rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .init_pci = clipper_init_pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .kill_arch = tsunami_kill_arch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .pci_map_irq = clipper_map_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .pci_swizzle = common_swizzle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) /* Sharks strongly resemble Clipper, at least as far
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) * as interrupt routing, etc, so we're using the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) * same functions as Clipper does
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) struct alpha_machine_vector shark_mv __initmv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .vector_name = "Shark",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) DO_EV6_MMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) DO_DEFAULT_RTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) DO_TSUNAMI_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .machine_check = tsunami_machine_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .min_io_address = DEFAULT_IO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .min_mem_address = DEFAULT_MEM_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .pci_dac_offset = TSUNAMI_DAC_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .nr_irqs = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .device_interrupt = dp264_device_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .init_arch = tsunami_init_arch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .init_irq = clipper_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .init_rtc = common_init_rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .init_pci = common_init_pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .kill_arch = tsunami_kill_arch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .pci_map_irq = clipper_map_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .pci_swizzle = common_swizzle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) /* No alpha_mv alias for webbrick/monet/clipper, since we compile them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) in unconditionally with DP264; setup_arch knows how to cope. */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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