^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/alpha/kernel/sys_cabriolet.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1995 David A Rusling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 1996 Jay A Estabrook
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 1998, 1999, 2000 Richard Henderson
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Code supporting the Cabriolet (AlphaPC64), EB66+, and EB164,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * PC164 and LX164.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/mmu_context.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/core_apecs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/core_cia.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/core_lca.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/tlbflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "proto.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include "irq_impl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include "pci_impl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include "machvec_impl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include "pc873xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* Note mask bit is true for DISABLED irqs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static unsigned long cached_irq_mask = ~0UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) cabriolet_update_irq_hw(unsigned int irq, unsigned long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) int ofs = (irq - 16) / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) outb(mask >> (16 + ofs * 8), 0x804 + ofs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) cabriolet_enable_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) cabriolet_update_irq_hw(d->irq, cached_irq_mask &= ~(1UL << d->irq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) cabriolet_disable_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) cabriolet_update_irq_hw(d->irq, cached_irq_mask |= 1UL << d->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static struct irq_chip cabriolet_irq_type = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .name = "CABRIOLET",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .irq_unmask = cabriolet_enable_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .irq_mask = cabriolet_disable_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .irq_mask_ack = cabriolet_disable_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) cabriolet_device_interrupt(unsigned long v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) unsigned long pld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* Read the interrupt summary registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) pld = inb(0x804) | (inb(0x805) << 8) | (inb(0x806) << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * Now for every possible bit set, work through them and call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * the appropriate interrupt handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) while (pld) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) i = ffz(~pld);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) pld &= pld - 1; /* clear least bit set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (i == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) isa_device_interrupt(v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) handle_irq(16 + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) common_init_irq(void (*srm_dev_int)(unsigned long v))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) init_i8259a_irqs();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (alpha_using_srm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) alpha_mv.device_interrupt = srm_dev_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) init_srm_irqs(35, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) long i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) outb(0xff, 0x804);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) outb(0xff, 0x805);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) outb(0xff, 0x806);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) for (i = 16; i < 35; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) irq_set_chip_and_handler(i, &cabriolet_irq_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) irq_set_status_flags(i, IRQ_LEVEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) common_init_isa_dma();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (request_irq(16 + 4, no_action, 0, "isa-cascade", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) pr_err("Failed to register isa-cascade interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #ifndef CONFIG_ALPHA_PC164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) cabriolet_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) common_init_irq(srm_device_interrupt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_PC164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* In theory, the PC164 has the same interrupt hardware as the other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) Cabriolet based systems. However, something got screwed up late
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) in the development cycle which broke the interrupt masking hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) Repeat, it is not possible to mask and ack interrupts. At all.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) In an attempt to work around this, while processing interrupts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) we do not allow the IPL to drop below what it is currently. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) prevents the possibility of recursion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) ??? Another option might be to force all PCI devices to use edge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) triggered rather than level triggered interrupts. That might be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) too invasive though. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) pc164_srm_device_interrupt(unsigned long v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) __min_ipl = getipl();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) srm_device_interrupt(v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) __min_ipl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) pc164_device_interrupt(unsigned long v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) __min_ipl = getipl();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) cabriolet_device_interrupt(v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) __min_ipl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) pc164_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) common_init_irq(pc164_srm_device_interrupt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * The EB66+ is very similar to the EB66 except that it does not have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * the on-board NCR and Tulip chips. In the code below, I have used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * slot number to refer to the id select line and *not* the slot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * number used in the EB66+ documentation. However, in the table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * I've given the slot number, the id select line and the Jxx number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * that's printed on the board. The interrupt pins from the PCI slots
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * are wired into 3 interrupt summary registers at 0x804, 0x805 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * 0x806 ISA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * In the table, -1 means don't assign an IRQ number. This is usually
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * because it is the Saturn IO (SIO) PCI/ISA Bridge Chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) eb66p_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static char irq_tab[5][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /*INT INTA INTB INTC INTD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {16+0, 16+0, 16+5, 16+9, 16+13}, /* IdSel 6, slot 0, J25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {16+1, 16+1, 16+6, 16+10, 16+14}, /* IdSel 7, slot 1, J26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) { -1, -1, -1, -1, -1}, /* IdSel 8, SIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {16+2, 16+2, 16+7, 16+11, 16+15}, /* IdSel 9, slot 2, J27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {16+3, 16+3, 16+8, 16+12, 16+6} /* IdSel 10, slot 3, J28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) const long min_idsel = 6, max_idsel = 10, irqs_per_slot = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return COMMON_TABLE_LOOKUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * The AlphaPC64 is very similar to the EB66+ except that its slots
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * are numbered differently. In the code below, I have used slot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * number to refer to the id select line and *not* the slot number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * used in the AlphaPC64 documentation. However, in the table, I've
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * given the slot number, the id select line and the Jxx number that's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * printed on the board. The interrupt pins from the PCI slots are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * wired into 3 interrupt summary registers at 0x804, 0x805 and 0x806
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * ISA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * In the table, -1 means don't assign an IRQ number. This is usually
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * because it is the Saturn IO (SIO) PCI/ISA Bridge Chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) cabriolet_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static char irq_tab[5][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /*INT INTA INTB INTC INTD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) { 16+2, 16+2, 16+7, 16+11, 16+15}, /* IdSel 5, slot 2, J21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) { 16+0, 16+0, 16+5, 16+9, 16+13}, /* IdSel 6, slot 0, J19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) { 16+1, 16+1, 16+6, 16+10, 16+14}, /* IdSel 7, slot 1, J20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) { -1, -1, -1, -1, -1}, /* IdSel 8, SIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) { 16+3, 16+3, 16+8, 16+12, 16+16} /* IdSel 9, slot 3, J22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) const long min_idsel = 5, max_idsel = 9, irqs_per_slot = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return COMMON_TABLE_LOOKUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static inline void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) cabriolet_enable_ide(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (pc873xx_probe() == -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) printk(KERN_ERR "Probing for PC873xx Super IO chip failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) printk(KERN_INFO "Found %s Super IO chip at 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) pc873xx_get_model(), pc873xx_get_base());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) pc873xx_enable_ide();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static inline void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) cabriolet_init_pci(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) common_init_pci();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) cabriolet_enable_ide();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static inline void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) cia_cab_init_pci(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) cia_init_pci();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) cabriolet_enable_ide();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * The PC164 and LX164 have 19 PCI interrupts, four from each of the four
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * PCI slots, the SIO, PCI/IDE, and USB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * Each of the interrupts can be individually masked. This is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * accomplished by setting the appropriate bit in the mask register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * A bit is set by writing a "1" to the desired position in the mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * register and cleared by writing a "0". There are 3 mask registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * located at ISA address 804h, 805h and 806h.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * An I/O read at ISA address 804h, 805h, 806h will return the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * state of the 11 PCI interrupts and not the state of the MASKED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * Note: A write to I/O 804h, 805h, and 806h the mask register will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * updated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * ISA DATA<7:0>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * ISA +--------------------------------------------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * ADDRESS | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * +==============================================================+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * 0x804 | INTB0 | USB | IDE | SIO | INTA3 |INTA2 | INTA1 | INTA0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * +--------------------------------------------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * 0x805 | INTD0 | INTC3 | INTC2 | INTC1 | INTC0 |INTB3 | INTB2 | INTB1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * +--------------------------------------------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * 0x806 | Rsrv | Rsrv | Rsrv | Rsrv | Rsrv |INTD3 | INTD2 | INTD1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * +--------------------------------------------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * * Rsrv = reserved bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * Note: The mask register is write-only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * IdSel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * 5 32 bit PCI option slot 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * 6 64 bit PCI option slot 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * 7 64 bit PCI option slot 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * 8 Saturn I/O
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * 9 32 bit PCI option slot 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * 10 USB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * 11 IDE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) alphapc164_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static char irq_tab[7][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /*INT INTA INTB INTC INTD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) { 16+2, 16+2, 16+9, 16+13, 16+17}, /* IdSel 5, slot 2, J20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) { 16+0, 16+0, 16+7, 16+11, 16+15}, /* IdSel 6, slot 0, J29 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) { 16+1, 16+1, 16+8, 16+12, 16+16}, /* IdSel 7, slot 1, J26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) { -1, -1, -1, -1, -1}, /* IdSel 8, SIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) { 16+3, 16+3, 16+10, 16+14, 16+18}, /* IdSel 9, slot 3, J19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) { 16+6, 16+6, 16+6, 16+6, 16+6}, /* IdSel 10, USB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) { 16+5, 16+5, 16+5, 16+5, 16+5} /* IdSel 11, IDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) const long min_idsel = 5, max_idsel = 11, irqs_per_slot = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return COMMON_TABLE_LOOKUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static inline void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) alphapc164_init_pci(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) cia_init_pci();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) SMC93x_Init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * The System Vector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_CABRIOLET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct alpha_machine_vector cabriolet_mv __initmv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .vector_name = "Cabriolet",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) DO_EV4_MMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) DO_DEFAULT_RTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) DO_APECS_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .machine_check = apecs_machine_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .min_io_address = DEFAULT_IO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .nr_irqs = 35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .device_interrupt = cabriolet_device_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .init_arch = apecs_init_arch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .init_irq = cabriolet_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .init_rtc = common_init_rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .init_pci = cabriolet_init_pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .pci_map_irq = cabriolet_map_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .pci_swizzle = common_swizzle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #ifndef CONFIG_ALPHA_EB64P
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) ALIAS_MV(cabriolet)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_EB164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct alpha_machine_vector eb164_mv __initmv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .vector_name = "EB164",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) DO_EV5_MMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) DO_DEFAULT_RTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) DO_CIA_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .machine_check = cia_machine_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .min_io_address = DEFAULT_IO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .min_mem_address = CIA_DEFAULT_MEM_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .nr_irqs = 35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .device_interrupt = cabriolet_device_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .init_arch = cia_init_arch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .init_irq = cabriolet_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .init_rtc = common_init_rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .init_pci = cia_cab_init_pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .kill_arch = cia_kill_arch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .pci_map_irq = cabriolet_map_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .pci_swizzle = common_swizzle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) ALIAS_MV(eb164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_EB66P)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct alpha_machine_vector eb66p_mv __initmv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .vector_name = "EB66+",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) DO_EV4_MMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) DO_DEFAULT_RTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) DO_LCA_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .machine_check = lca_machine_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .min_io_address = DEFAULT_IO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .nr_irqs = 35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .device_interrupt = cabriolet_device_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .init_arch = lca_init_arch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .init_irq = cabriolet_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .init_rtc = common_init_rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .init_pci = cabriolet_init_pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .pci_map_irq = eb66p_map_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .pci_swizzle = common_swizzle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) ALIAS_MV(eb66p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_LX164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct alpha_machine_vector lx164_mv __initmv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .vector_name = "LX164",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) DO_EV5_MMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) DO_DEFAULT_RTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) DO_PYXIS_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .machine_check = cia_machine_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .min_io_address = DEFAULT_IO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .min_mem_address = DEFAULT_MEM_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .pci_dac_offset = PYXIS_DAC_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .nr_irqs = 35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .device_interrupt = cabriolet_device_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .init_arch = pyxis_init_arch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .init_irq = cabriolet_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .init_rtc = common_init_rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .init_pci = alphapc164_init_pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .kill_arch = cia_kill_arch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .pci_map_irq = alphapc164_map_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .pci_swizzle = common_swizzle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) ALIAS_MV(lx164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_PC164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) struct alpha_machine_vector pc164_mv __initmv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .vector_name = "PC164",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) DO_EV5_MMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) DO_DEFAULT_RTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) DO_CIA_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .machine_check = cia_machine_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .min_io_address = DEFAULT_IO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .min_mem_address = CIA_DEFAULT_MEM_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .nr_irqs = 35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .device_interrupt = pc164_device_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .init_arch = cia_init_arch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .init_irq = pc164_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .init_rtc = common_init_rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .init_pci = alphapc164_init_pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .kill_arch = cia_kill_arch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .pci_map_irq = alphapc164_map_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .pci_swizzle = common_swizzle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) ALIAS_MV(pc164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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