^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * SMC 37C93X initialization code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/hwrpb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define SMC_DEBUG 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #if SMC_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) # define DBG_DEVS(args) printk args
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) # define DBG_DEVS(args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define KB 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MB (1024*KB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define GB (1024*MB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* device "activate" register contents */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DEVICE_ON 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DEVICE_OFF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* configuration on/off keys */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CONFIG_ON_KEY 0x55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CONFIG_OFF_KEY 0xaa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* configuration space device definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define FDC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define IDE1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define IDE2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PARP 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SER1 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SER2 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define RTCL 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define KYBD 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define AUXIO 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* Chip register offsets from base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CONFIG_CONTROL 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define INDEX_ADDRESS 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define LOGICAL_DEVICE_NUMBER 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DEVICE_ID 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DEVICE_REV 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define POWER_CONTROL 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define POWER_MGMT 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define OSC 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ACTIVATE 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ADDR_HI 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ADDR_LO 0x61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define INTERRUPT_SEL 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define INTERRUPT_SEL_2 0x72 /* KYBD/MOUS only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define DMA_CHANNEL_SEL 0x74 /* FDC/PARP only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define FDD_MODE_REGISTER 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define FDD_OPTION_REGISTER 0x91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* values that we read back that are expected ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define VALID_DEVICE_ID 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* default device addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define KYBD_INTERRUPT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MOUS_INTERRUPT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define COM2_BASE 0x2f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define COM2_INTERRUPT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define COM1_BASE 0x3f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define COM1_INTERRUPT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PARP_BASE 0x3bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define PARP_INTERRUPT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static unsigned long __init SMCConfigState(unsigned long baseAddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) unsigned char devId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) unsigned long configPort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) unsigned long indexPort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) unsigned long dataPort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) configPort = indexPort = baseAddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) dataPort = configPort + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define NUM_RETRIES 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) for (i = 0; i < NUM_RETRIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) outb(CONFIG_ON_KEY, configPort);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) outb(CONFIG_ON_KEY, configPort);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) outb(DEVICE_ID, indexPort);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) devId = inb(dataPort);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (devId == VALID_DEVICE_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) outb(DEVICE_REV, indexPort);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* unsigned char devRev = */ inb(dataPort);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return (i != NUM_RETRIES) ? baseAddr : 0L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static void __init SMCRunState(unsigned long baseAddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) outb(CONFIG_OFF_KEY, baseAddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static unsigned long __init SMCDetectUltraIO(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned long baseAddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) baseAddr = 0x3F0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if ( ( baseAddr = SMCConfigState( baseAddr ) ) == 0x3F0 ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return( baseAddr );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) baseAddr = 0x370;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if ( ( baseAddr = SMCConfigState( baseAddr ) ) == 0x370 ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return( baseAddr );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return( ( unsigned long )0 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static void __init SMCEnableDevice(unsigned long baseAddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) unsigned long device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) unsigned long portaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) unsigned long interrupt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) unsigned long indexPort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) unsigned long dataPort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) indexPort = baseAddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) dataPort = baseAddr + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) outb(LOGICAL_DEVICE_NUMBER, indexPort);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) outb(device, dataPort);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) outb(ADDR_LO, indexPort);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) outb(( portaddr & 0xFF ), dataPort);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) outb(ADDR_HI, indexPort);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) outb((portaddr >> 8) & 0xFF, dataPort);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) outb(INTERRUPT_SEL, indexPort);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) outb(interrupt, dataPort);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) outb(ACTIVATE, indexPort);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) outb(DEVICE_ON, dataPort);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static void __init SMCEnableKYBD(unsigned long baseAddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) unsigned long indexPort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) unsigned long dataPort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) indexPort = baseAddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) dataPort = baseAddr + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) outb(LOGICAL_DEVICE_NUMBER, indexPort);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) outb(KYBD, dataPort);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) outb(INTERRUPT_SEL, indexPort); /* Primary interrupt select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) outb(KYBD_INTERRUPT, dataPort);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) outb(INTERRUPT_SEL_2, indexPort); /* Secondary interrupt select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) outb(MOUS_INTERRUPT, dataPort);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) outb(ACTIVATE, indexPort);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) outb(DEVICE_ON, dataPort);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static void __init SMCEnableFDC(unsigned long baseAddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) unsigned long indexPort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) unsigned long dataPort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) unsigned char oldValue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) indexPort = baseAddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) dataPort = baseAddr + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) outb(LOGICAL_DEVICE_NUMBER, indexPort);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) outb(FDC, dataPort);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) outb(FDD_MODE_REGISTER, indexPort);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) oldValue = inb(dataPort);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) oldValue |= 0x0E; /* Enable burst mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) outb(oldValue, dataPort);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) outb(INTERRUPT_SEL, indexPort); /* Primary interrupt select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) outb(0x06, dataPort );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) outb(DMA_CHANNEL_SEL, indexPort); /* DMA channel select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) outb(0x02, dataPort);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) outb(ACTIVATE, indexPort);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) outb(DEVICE_ON, dataPort);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #if SMC_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static void __init SMCReportDeviceStatus(unsigned long baseAddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) unsigned long indexPort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) unsigned long dataPort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) unsigned char currentControl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) indexPort = baseAddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) dataPort = baseAddr + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) outb(POWER_CONTROL, indexPort);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) currentControl = inb(dataPort);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) printk(currentControl & (1 << FDC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ? "\t+FDC Enabled\n" : "\t-FDC Disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) printk(currentControl & (1 << IDE1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) ? "\t+IDE1 Enabled\n" : "\t-IDE1 Disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) printk(currentControl & (1 << IDE2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) ? "\t+IDE2 Enabled\n" : "\t-IDE2 Disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) printk(currentControl & (1 << PARP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ? "\t+PARP Enabled\n" : "\t-PARP Disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) printk(currentControl & (1 << SER1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ? "\t+SER1 Enabled\n" : "\t-SER1 Disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) printk(currentControl & (1 << SER2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) ? "\t+SER2 Enabled\n" : "\t-SER2 Disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) printk( "\n" );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) int __init SMC93x_Init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) unsigned long SMCUltraBase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if ((SMCUltraBase = SMCDetectUltraIO()) != 0UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #if SMC_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) SMCReportDeviceStatus(SMCUltraBase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) SMCEnableDevice(SMCUltraBase, SER1, COM1_BASE, COM1_INTERRUPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) DBG_DEVS(("SMC FDC37C93X: SER1 done\n"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) SMCEnableDevice(SMCUltraBase, SER2, COM2_BASE, COM2_INTERRUPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) DBG_DEVS(("SMC FDC37C93X: SER2 done\n"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) SMCEnableDevice(SMCUltraBase, PARP, PARP_BASE, PARP_INTERRUPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) DBG_DEVS(("SMC FDC37C93X: PARP done\n"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* On PC164, IDE on the SMC is not enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) CMD646 (PCI) on MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) SMCEnableKYBD(SMCUltraBase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) DBG_DEVS(("SMC FDC37C93X: KYB done\n"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) SMCEnableFDC(SMCUltraBase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) DBG_DEVS(("SMC FDC37C93X: FDC done\n"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #if SMC_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) SMCReportDeviceStatus(SMCUltraBase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) SMCRunState(SMCUltraBase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) printk("SMC FDC37C93X Ultra I/O Controller found @ 0x%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) SMCUltraBase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) DBG_DEVS(("No SMC FDC37C93X Ultra I/O Controller found\n"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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