^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * SMC 37C669 initialization code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/hwrpb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) # define DBG_DEVS(args) printk args
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) # define DBG_DEVS(args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define KB 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MB (1024*KB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define GB (1024*MB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SMC_DEBUG 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* File: smcc669_def.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * Copyright (C) 1997 by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * Digital Equipment Corporation, Maynard, Massachusetts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * This software is furnished under a license and may be used and copied
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * only in accordance of the terms of such license and with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * inclusion of the above copyright notice. This software or any other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * copies thereof may not be provided or otherwise made available to any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * other person. No title to and ownership of the software is hereby
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * transferred.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * The information in this software is subject to change without notice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * and should not be construed as a commitment by Digital Equipment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * Digital assumes no responsibility for the use or reliability of its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * software on equipment which is not supplied by Digital.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * Abstract:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * This file contains header definitions for the SMC37c669
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * Super I/O controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * Author:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * Eric Rasmussen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * Modification History:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * er 28-Jan-1997 Initial Entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #ifndef __SMC37c669_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define __SMC37c669_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) ** Macros for handling device IRQs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) ** The mask acts as a flag used in mapping actual ISA IRQs (0 - 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) ** to device IRQs (A - H).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SMC37c669_DEVICE_IRQ_MASK 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SMC37c669_DEVICE_IRQ( __i ) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) ((SMC37c669_DEVICE_IRQ_MASK) | (__i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SMC37c669_IS_DEVICE_IRQ(__i) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) (((__i) & (SMC37c669_DEVICE_IRQ_MASK)) == (SMC37c669_DEVICE_IRQ_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SMC37c669_RAW_DEVICE_IRQ(__i) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ((__i) & ~(SMC37c669_DEVICE_IRQ_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ** Macros for handling device DRQs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) ** The mask acts as a flag used in mapping actual ISA DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ** channels to device DMA channels (A - C).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SMC37c669_DEVICE_DRQ_MASK 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SMC37c669_DEVICE_DRQ(__d) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) ((SMC37c669_DEVICE_DRQ_MASK) | (__d))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SMC37c669_IS_DEVICE_DRQ(__d) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) (((__d) & (SMC37c669_DEVICE_DRQ_MASK)) == (SMC37c669_DEVICE_DRQ_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SMC37c669_RAW_DEVICE_DRQ(__d) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ((__d) & ~(SMC37c669_DEVICE_DRQ_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SMC37c669_DEVICE_ID 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) ** SMC37c669 Device Function Definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SERIAL_0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SERIAL_1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define PARALLEL_0 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define FLOPPY_0 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define IDE_0 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define NUM_FUNCS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ** Default Device Function Mappings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define COM1_BASE 0x3F8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define COM1_IRQ 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define COM2_BASE 0x2F8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define COM2_IRQ 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define PARP_BASE 0x3BC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define PARP_IRQ 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define PARP_DRQ 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define FDC_BASE 0x3F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define FDC_IRQ 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define FDC_DRQ 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) ** Configuration On/Off Key Definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SMC37c669_CONFIG_ON_KEY 0x55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SMC37c669_CONFIG_OFF_KEY 0xAA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) ** SMC 37c669 Device IRQs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SMC37c669_DEVICE_IRQ_A ( SMC37c669_DEVICE_IRQ( 0x01 ) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SMC37c669_DEVICE_IRQ_B ( SMC37c669_DEVICE_IRQ( 0x02 ) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SMC37c669_DEVICE_IRQ_C ( SMC37c669_DEVICE_IRQ( 0x03 ) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SMC37c669_DEVICE_IRQ_D ( SMC37c669_DEVICE_IRQ( 0x04 ) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define SMC37c669_DEVICE_IRQ_E ( SMC37c669_DEVICE_IRQ( 0x05 ) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SMC37c669_DEVICE_IRQ_F ( SMC37c669_DEVICE_IRQ( 0x06 ) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* SMC37c669_DEVICE_IRQ_G *** RESERVED ***/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SMC37c669_DEVICE_IRQ_H ( SMC37c669_DEVICE_IRQ( 0x08 ) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ** SMC 37c669 Device DMA Channel Definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define SMC37c669_DEVICE_DRQ_A ( SMC37c669_DEVICE_DRQ( 0x01 ) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SMC37c669_DEVICE_DRQ_B ( SMC37c669_DEVICE_DRQ( 0x02 ) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define SMC37c669_DEVICE_DRQ_C ( SMC37c669_DEVICE_DRQ( 0x03 ) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) ** Configuration Register Index Definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SMC37c669_CR00_INDEX 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define SMC37c669_CR01_INDEX 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define SMC37c669_CR02_INDEX 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define SMC37c669_CR03_INDEX 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define SMC37c669_CR04_INDEX 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define SMC37c669_CR05_INDEX 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define SMC37c669_CR06_INDEX 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define SMC37c669_CR07_INDEX 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define SMC37c669_CR08_INDEX 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define SMC37c669_CR09_INDEX 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define SMC37c669_CR0A_INDEX 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define SMC37c669_CR0B_INDEX 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define SMC37c669_CR0C_INDEX 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define SMC37c669_CR0D_INDEX 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define SMC37c669_CR0E_INDEX 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define SMC37c669_CR0F_INDEX 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define SMC37c669_CR10_INDEX 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define SMC37c669_CR11_INDEX 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define SMC37c669_CR12_INDEX 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define SMC37c669_CR13_INDEX 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define SMC37c669_CR14_INDEX 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define SMC37c669_CR15_INDEX 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define SMC37c669_CR16_INDEX 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define SMC37c669_CR17_INDEX 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define SMC37c669_CR18_INDEX 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define SMC37c669_CR19_INDEX 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define SMC37c669_CR1A_INDEX 0x1A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define SMC37c669_CR1B_INDEX 0x1B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define SMC37c669_CR1C_INDEX 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define SMC37c669_CR1D_INDEX 0x1D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define SMC37c669_CR1E_INDEX 0x1E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define SMC37c669_CR1F_INDEX 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define SMC37c669_CR20_INDEX 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define SMC37c669_CR21_INDEX 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define SMC37c669_CR22_INDEX 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define SMC37c669_CR23_INDEX 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define SMC37c669_CR24_INDEX 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define SMC37c669_CR25_INDEX 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define SMC37c669_CR26_INDEX 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define SMC37c669_CR27_INDEX 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define SMC37c669_CR28_INDEX 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define SMC37c669_CR29_INDEX 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ** Configuration Register Alias Definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define SMC37c669_DEVICE_ID_INDEX SMC37c669_CR0D_INDEX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define SMC37c669_DEVICE_REVISION_INDEX SMC37c669_CR0E_INDEX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define SMC37c669_FDC_BASE_ADDRESS_INDEX SMC37c669_CR20_INDEX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define SMC37c669_IDE_BASE_ADDRESS_INDEX SMC37c669_CR21_INDEX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define SMC37c669_IDE_ALTERNATE_ADDRESS_INDEX SMC37c669_CR22_INDEX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define SMC37c669_PARALLEL0_BASE_ADDRESS_INDEX SMC37c669_CR23_INDEX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define SMC37c669_SERIAL0_BASE_ADDRESS_INDEX SMC37c669_CR24_INDEX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define SMC37c669_SERIAL1_BASE_ADDRESS_INDEX SMC37c669_CR25_INDEX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define SMC37c669_PARALLEL_FDC_DRQ_INDEX SMC37c669_CR26_INDEX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define SMC37c669_PARALLEL_FDC_IRQ_INDEX SMC37c669_CR27_INDEX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define SMC37c669_SERIAL_IRQ_INDEX SMC37c669_CR28_INDEX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) ** Configuration Register Definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) ** The INDEX (write only) and DATA (read/write) ports are effective
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ** only when the chip is in the Configuration State.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) typedef struct _SMC37c669_CONFIG_REGS {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) unsigned char index_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) unsigned char data_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) } SMC37c669_CONFIG_REGS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) ** CR00 - default value 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) ** IDE_EN (CR00<1:0>):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) ** 0x - 30ua pull-ups on nIDEEN, nHDCS0, NHDCS1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ** 11 - IRQ_H available as IRQ output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ** IRRX2, IRTX2 available as alternate IR pins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ** 10 - nIDEEN, nHDCS0, nHDCS1 used to control IDE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) ** VALID (CR00<7>):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) ** A high level on this software controlled bit can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) ** be used to indicate that a valid configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) ** cycle has occurred. The control software must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ** take care to set this bit at the appropriate times.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) ** Set to zero after power up. This bit has no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ** effect on any other hardware in the chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) typedef union _SMC37c669_CR00 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) unsigned char as_uchar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) unsigned ide_en : 2; /* See note above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) unsigned reserved1 : 1; /* RAZ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) unsigned fdc_pwr : 1; /* 1 = supply power to FDC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) unsigned reserved2 : 3; /* Read as 010b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) unsigned valid : 1; /* See note above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) } by_field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) } SMC37c669_CR00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ** CR01 - default value 0x9C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) typedef union _SMC37c669_CR01 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) unsigned char as_uchar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) unsigned reserved1 : 2; /* RAZ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) unsigned ppt_pwr : 1; /* 1 = supply power to PPT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) unsigned ppt_mode : 1; /* 1 = Printer mode, 0 = EPP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) unsigned reserved2 : 1; /* Read as 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) unsigned reserved3 : 2; /* RAZ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) unsigned lock_crx: 1; /* Lock CR00 - CR18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) } by_field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) } SMC37c669_CR01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) ** CR02 - default value 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) typedef union _SMC37c669_CR02 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) unsigned char as_uchar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) unsigned reserved1 : 3; /* RAZ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) unsigned uart1_pwr : 1; /* 1 = supply power to UART1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) unsigned reserved2 : 3; /* RAZ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) unsigned uart2_pwr : 1; /* 1 = supply power to UART2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) } by_field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) } SMC37c669_CR02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) ** CR03 - default value 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) ** CR03<7> CR03<2> Pin 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) ** ------- ------- ------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) ** 0 X DRV2 (input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) ** 1 0 ADRX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) ** 1 1 IRQ_B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) ** CR03<6> CR03<5> Op Mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) ** ------- ------- -------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) ** 0 0 Model 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) ** 0 1 PS/2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) ** 1 0 Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) ** 1 1 AT Mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) typedef union _SMC37c669_CR03 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) unsigned char as_uchar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) unsigned pwrgd_gamecs : 1; /* 1 = PWRGD, 0 = GAMECS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) unsigned fdc_mode2 : 1; /* 1 = Enhanced Mode 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) unsigned pin94_0 : 1; /* See note above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) unsigned reserved1 : 1; /* RAZ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) unsigned drvden : 1; /* 1 = high, 0 - output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) unsigned op_mode : 2; /* See note above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) unsigned pin94_1 : 1; /* See note above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) } by_field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) } SMC37c669_CR03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) ** CR04 - default value 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) ** PP_EXT_MODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) ** If CR01<PP_MODE> = 0 and PP_EXT_MODE =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) ** 00 - Standard and Bidirectional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ** 01 - EPP mode and SPP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) ** 10 - ECP mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) ** In this mode, 2 drives can be supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) ** directly, 3 or 4 drives must use external
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) ** 4 drive support. SPP can be selected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) ** through the ECR register of ECP as mode 000.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ** 11 - ECP mode and EPP mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) ** In this mode, 2 drives can be supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ** directly, 3 or 4 drives must use external
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) ** 4 drive support. SPP can be selected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) ** through the ECR register of ECP as mode 000.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) ** In this mode, EPP can be selected through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) ** the ECR register of ECP as mode 100.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) ** PP_FDC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) ** 00 - Normal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) ** 01 - PPFD1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) ** 10 - PPFD2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) ** 11 - Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) ** MIDI1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) ** Serial Clock Select:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) ** A low level on this bit disables MIDI support,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) ** clock = divide by 13. A high level on this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) ** bit enables MIDI support, clock = divide by 12.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) ** MIDI operates at 31.25 Kbps which can be derived
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) ** from 125 KHz (24 MHz / 12 = 2 MHz, 2 MHz / 16 = 125 KHz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) ** ALT_IO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) ** 0 - Use pins IRRX, IRTX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) ** 1 - Use pins IRRX2, IRTX2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) ** If this bit is set, the IR receive and transmit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) ** functions will not be available on pins 25 and 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) ** unless CR00<IDE_EN> = 11.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) typedef union _SMC37c669_CR04 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) unsigned char as_uchar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) unsigned ppt_ext_mode : 2; /* See note above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) unsigned ppt_fdc : 2; /* See note above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) unsigned midi1 : 1; /* See note above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) unsigned midi2 : 1; /* See note above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) unsigned epp_type : 1; /* 0 = EPP 1.9, 1 = EPP 1.7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) unsigned alt_io : 1; /* See note above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) } by_field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) } SMC37c669_CR04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) ** CR05 - default value 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) ** DEN_SEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) ** 00 - Densel output normal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) ** 01 - Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) ** 10 - Densel output 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) ** 11 - Densel output 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) typedef union _SMC37c669_CR05 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) unsigned char as_uchar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) unsigned reserved1 : 2; /* RAZ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) unsigned fdc_dma_mode : 1; /* 0 = burst, 1 = non-burst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) unsigned den_sel : 2; /* See note above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) unsigned swap_drv : 1; /* Swap the FDC motor selects */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) unsigned extx4 : 1; /* 0 = 2 drive, 1 = external 4 drive decode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) unsigned reserved2 : 1; /* RAZ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) } by_field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) } SMC37c669_CR05;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) ** CR06 - default value 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) typedef union _SMC37c669_CR06 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) unsigned char as_uchar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) unsigned floppy_a : 2; /* Type of floppy drive A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) unsigned floppy_b : 2; /* Type of floppy drive B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) unsigned floppy_c : 2; /* Type of floppy drive C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) unsigned floppy_d : 2; /* Type of floppy drive D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) } by_field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) } SMC37c669_CR06;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) ** CR07 - default value 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ** Auto Power Management CR07<7:4>:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) ** 0 - Auto Powerdown disabled (default)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) ** 1 - Auto Powerdown enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) ** This bit is reset to the default state by POR or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) ** a hardware reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) typedef union _SMC37c669_CR07 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) unsigned char as_uchar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) unsigned floppy_boot : 2; /* 0 = A:, 1 = B: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) unsigned reserved1 : 2; /* RAZ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) unsigned ppt_en : 1; /* See note above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) unsigned uart1_en : 1; /* See note above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) unsigned uart2_en : 1; /* See note above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) unsigned fdc_en : 1; /* See note above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) } by_field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) } SMC37c669_CR07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) ** CR08 - default value 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) typedef union _SMC37c669_CR08 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) unsigned char as_uchar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) unsigned zero : 4; /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) unsigned addrx7_4 : 4; /* ADR<7:3> for ADRx decode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) } by_field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) } SMC37c669_CR08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) ** CR09 - default value 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) ** ADRx_CONFIG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) ** 00 - ADRx disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) ** 01 - 1 byte decode A<3:0> = 0000b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) ** 10 - 8 byte block decode A<3:0> = 0XXXb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) ** 11 - 16 byte block decode A<3:0> = XXXXb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) typedef union _SMC37c669_CR09 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) unsigned char as_uchar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) unsigned adra8 : 3; /* ADR<10:8> for ADRx decode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) unsigned reserved1 : 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) unsigned adrx_config : 2; /* See note above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) } by_field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) } SMC37c669_CR09;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) ** CR0A - default value 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) typedef union _SMC37c669_CR0A {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) unsigned char as_uchar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) unsigned ecp_fifo_threshold : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) unsigned reserved1 : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) } by_field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) } SMC37c669_CR0A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) ** CR0B - default value 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) typedef union _SMC37c669_CR0B {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) unsigned char as_uchar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) unsigned fdd0_drtx : 2; /* FDD0 Data Rate Table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) unsigned fdd1_drtx : 2; /* FDD1 Data Rate Table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) unsigned fdd2_drtx : 2; /* FDD2 Data Rate Table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) unsigned fdd3_drtx : 2; /* FDD3 Data Rate Table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) } by_field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) } SMC37c669_CR0B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) ** CR0C - default value 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) ** UART2_MODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) ** 000 - Standard (default)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) ** 001 - IrDA (HPSIR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) ** 010 - Amplitude Shift Keyed IR @500 KHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) ** 011 - Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) ** 1xx - Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) typedef union _SMC37c669_CR0C {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) unsigned char as_uchar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) unsigned uart2_rcv_polarity : 1; /* 1 = invert RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) unsigned uart2_xmit_polarity : 1; /* 1 = invert TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) unsigned uart2_duplex : 1; /* 1 = full, 0 = half */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) unsigned uart2_mode : 3; /* See note above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) unsigned uart1_speed : 1; /* 1 = high speed enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) unsigned uart2_speed : 1; /* 1 = high speed enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) } by_field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) } SMC37c669_CR0C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) ** CR0D - default value 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) ** Device ID Register - read only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) typedef union _SMC37c669_CR0D {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) unsigned char as_uchar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) unsigned device_id : 8; /* Returns 0x3 in this field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) } by_field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) } SMC37c669_CR0D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) ** CR0E - default value 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) ** Device Revision Register - read only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) typedef union _SMC37c669_CR0E {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) unsigned char as_uchar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) unsigned device_rev : 8; /* Returns 0x2 in this field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) } by_field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) } SMC37c669_CR0E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) ** CR0F - default value 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) typedef union _SMC37c669_CR0F {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) unsigned char as_uchar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) unsigned test0 : 1; /* Reserved - set to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) unsigned test1 : 1; /* Reserved - set to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) unsigned test2 : 1; /* Reserved - set to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) unsigned test3 : 1; /* Reserved - set t0 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) unsigned test4 : 1; /* Reserved - set to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) unsigned test5 : 1; /* Reserved - set t0 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) unsigned test6 : 1; /* Reserved - set t0 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) unsigned test7 : 1; /* Reserved - set to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) } by_field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) } SMC37c669_CR0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) ** CR10 - default value 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) typedef union _SMC37c669_CR10 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) unsigned char as_uchar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) unsigned reserved1 : 3; /* RAZ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) unsigned pll_gain : 1; /* 1 = 3V, 2 = 5V operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) unsigned pll_stop : 1; /* 1 = stop PLLs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) unsigned ace_stop : 1; /* 1 = stop UART clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) unsigned pll_clock_ctrl : 1; /* 0 = 14.318 MHz, 1 = 24 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) unsigned ir_test : 1; /* Enable IR test mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) } by_field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) } SMC37c669_CR10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) ** CR11 - default value 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) typedef union _SMC37c669_CR11 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) unsigned char as_uchar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) unsigned ir_loopback : 1; /* Internal IR loop back */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) unsigned test_10ms : 1; /* Test 10ms autopowerdown FDC timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) unsigned reserved1 : 6; /* RAZ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) } by_field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) } SMC37c669_CR11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) ** CR12 - CR1D are reserved registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) ** CR1E - default value 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) ** GAMECS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) ** 00 - GAMECS disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) ** 01 - 1 byte decode ADR<3:0> = 0001b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) ** 10 - 8 byte block decode ADR<3:0> = 0XXXb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) ** 11 - 16 byte block decode ADR<3:0> = XXXXb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) typedef union _SMC37c66_CR1E {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) unsigned char as_uchar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) unsigned gamecs_config: 2; /* See note above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) unsigned gamecs_addr9_4 : 6; /* GAMECS Addr<9:4> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) } by_field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) } SMC37c669_CR1E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) ** CR1F - default value 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) ** DT0 DT1 DRVDEN0 DRVDEN1 Drive Type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) ** --- --- ------- ------- ----------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) ** 0 0 DENSEL DRATE0 4/2/1 MB 3.5"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) ** 2/1 MB 5.25"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) ** 2/1.6/1 MB 3.5" (3-mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) ** 0 1 DRATE1 DRATE0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) ** 1 0 nDENSEL DRATE0 PS/2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) ** 1 1 DRATE0 DRATE1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) ** Note: DENSEL, DRATE1, and DRATE0 map onto two output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) ** pins - DRVDEN0 and DRVDEN1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) typedef union _SMC37c669_CR1F {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) unsigned char as_uchar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) unsigned fdd0_drive_type : 2; /* FDD0 drive type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) unsigned fdd1_drive_type : 2; /* FDD1 drive type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) unsigned fdd2_drive_type : 2; /* FDD2 drive type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) unsigned fdd3_drive_type : 2; /* FDD3 drive type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) } by_field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) } SMC37c669_CR1F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) ** CR20 - default value 0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) ** FDC Base Address Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) ** - To disable this decode set Addr<9:8> = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) ** - A<10> = 0, A<3:0> = 0XXXb to access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) typedef union _SMC37c669_CR20 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) unsigned char as_uchar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) unsigned zero : 2; /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) unsigned addr9_4 : 6; /* FDC Addr<9:4> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) } by_field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) } SMC37c669_CR20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) ** CR21 - default value 0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) ** IDE Base Address Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) ** - To disable this decode set Addr<9:8> = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) ** - A<10> = 0, A<3:0> = 0XXXb to access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) typedef union _SMC37c669_CR21 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) unsigned char as_uchar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) unsigned zero : 2; /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) unsigned addr9_4 : 6; /* IDE Addr<9:4> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) } by_field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) } SMC37c669_CR21;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) ** CR22 - default value 0x3D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) ** IDE Alternate Status Base Address Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) ** - To disable this decode set Addr<9:8> = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) ** - A<10> = 0, A<3:0> = 0110b to access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) typedef union _SMC37c669_CR22 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) unsigned char as_uchar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) unsigned zero : 2; /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) unsigned addr9_4 : 6; /* IDE Alt Status Addr<9:4> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) } by_field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) } SMC37c669_CR22;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) ** CR23 - default value 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) ** Parallel Port Base Address Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) ** - To disable this decode set Addr<9:8> = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) ** - A<10> = 0 to access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) ** - If EPP is enabled, A<2:0> = XXXb to access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) ** If EPP is NOT enabled, A<1:0> = XXb to access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) typedef union _SMC37c669_CR23 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) unsigned char as_uchar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) unsigned addr9_2 : 8; /* Parallel Port Addr<9:2> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) } by_field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) } SMC37c669_CR23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) ** CR24 - default value 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) ** UART1 Base Address Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) ** - To disable this decode set Addr<9:8> = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) ** - A<10> = 0, A<2:0> = XXXb to access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) typedef union _SMC37c669_CR24 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) unsigned char as_uchar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) unsigned zero : 1; /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) unsigned addr9_3 : 7; /* UART1 Addr<9:3> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) } by_field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) } SMC37c669_CR24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) ** CR25 - default value 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) ** UART2 Base Address Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) ** - To disable this decode set Addr<9:8> = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) ** - A<10> = 0, A<2:0> = XXXb to access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) typedef union _SMC37c669_CR25 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) unsigned char as_uchar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) unsigned zero : 1; /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) unsigned addr9_3 : 7; /* UART2 Addr<9:3> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) } by_field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) } SMC37c669_CR25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) ** CR26 - default value 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) ** Parallel Port / FDC DMA Select Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) ** D3 - D0 DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) ** D7 - D4 Selected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) ** ------- --------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) ** 0000 None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) ** 0001 DMA_A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) ** 0010 DMA_B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) ** 0011 DMA_C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) typedef union _SMC37c669_CR26 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) unsigned char as_uchar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) unsigned ppt_drq : 4; /* See note above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) unsigned fdc_drq : 4; /* See note above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) } by_field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) } SMC37c669_CR26;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) ** CR27 - default value 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) ** Parallel Port / FDC IRQ Select Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) ** D3 - D0 IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) ** D7 - D4 Selected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) ** ------- --------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) ** 0000 None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) ** 0001 IRQ_A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) ** 0010 IRQ_B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) ** 0011 IRQ_C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) ** 0100 IRQ_D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) ** 0101 IRQ_E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) ** 0110 IRQ_F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) ** 0111 Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) ** 1000 IRQ_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) ** Any unselected IRQ REQ is in tristate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) typedef union _SMC37c669_CR27 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) unsigned char as_uchar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) unsigned ppt_irq : 4; /* See note above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) unsigned fdc_irq : 4; /* See note above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) } by_field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) } SMC37c669_CR27;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) ** CR28 - default value 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) ** UART IRQ Select Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) ** D3 - D0 IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) ** D7 - D4 Selected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) ** ------- --------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) ** 0000 None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) ** 0001 IRQ_A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) ** 0010 IRQ_B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) ** 0011 IRQ_C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) ** 0100 IRQ_D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) ** 0101 IRQ_E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) ** 0110 IRQ_F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) ** 0111 Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) ** 1000 IRQ_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) ** 1111 share with UART1 (only for UART2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) ** Any unselected IRQ REQ is in tristate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) ** To share an IRQ between UART1 and UART2, set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) ** UART1 to use the desired IRQ and set UART2 to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) ** 0xF to enable sharing mechanism.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) typedef union _SMC37c669_CR28 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) unsigned char as_uchar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) unsigned uart2_irq : 4; /* See note above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) unsigned uart1_irq : 4; /* See note above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) } by_field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) } SMC37c669_CR28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) ** CR29 - default value 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) ** IRQIN IRQ Select Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) ** D3 - D0 IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) ** D7 - D4 Selected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) ** ------- --------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) ** 0000 None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) ** 0001 IRQ_A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) ** 0010 IRQ_B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) ** 0011 IRQ_C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) ** 0100 IRQ_D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) ** 0101 IRQ_E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) ** 0110 IRQ_F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) ** 0111 Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) ** 1000 IRQ_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) ** Any unselected IRQ REQ is in tristate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) typedef union _SMC37c669_CR29 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) unsigned char as_uchar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) unsigned irqin_irq : 4; /* See note above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) unsigned reserved1 : 4; /* RAZ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) } by_field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) } SMC37c669_CR29;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) ** Aliases of Configuration Register formats (should match
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) ** the set of index aliases).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) ** Note that CR24 and CR25 have the same format and are the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) ** base address registers for UART1 and UART2. Because of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) ** this we only define 1 alias here - for CR24 - as the serial
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) ** base address register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) ** Note that CR21 and CR22 have the same format and are the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) ** base address and alternate status address registers for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) ** the IDE controller. Because of this we only define 1 alias
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) ** here - for CR21 - as the IDE address register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) typedef SMC37c669_CR0D SMC37c669_DEVICE_ID_REGISTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) typedef SMC37c669_CR0E SMC37c669_DEVICE_REVISION_REGISTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) typedef SMC37c669_CR20 SMC37c669_FDC_BASE_ADDRESS_REGISTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) typedef SMC37c669_CR21 SMC37c669_IDE_ADDRESS_REGISTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) typedef SMC37c669_CR23 SMC37c669_PARALLEL_BASE_ADDRESS_REGISTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) typedef SMC37c669_CR24 SMC37c669_SERIAL_BASE_ADDRESS_REGISTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) typedef SMC37c669_CR26 SMC37c669_PARALLEL_FDC_DRQ_REGISTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) typedef SMC37c669_CR27 SMC37c669_PARALLEL_FDC_IRQ_REGISTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) typedef SMC37c669_CR28 SMC37c669_SERIAL_IRQ_REGISTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) ** ISA/Device IRQ Translation Table Entry Definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) typedef struct _SMC37c669_IRQ_TRANSLATION_ENTRY {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) int device_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) int isa_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) } SMC37c669_IRQ_TRANSLATION_ENTRY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) ** ISA/Device DMA Translation Table Entry Definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) typedef struct _SMC37c669_DRQ_TRANSLATION_ENTRY {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) int device_drq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) int isa_drq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) } SMC37c669_DRQ_TRANSLATION_ENTRY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) ** External Interface Function Prototype Declarations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) SMC37c669_CONFIG_REGS *SMC37c669_detect(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) unsigned int SMC37c669_enable_device(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) unsigned int func
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) unsigned int SMC37c669_disable_device(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) unsigned int func
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) unsigned int SMC37c669_configure_device(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) unsigned int func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) int drq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) void SMC37c669_display_device_info(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) #endif /* __SMC37c669_H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) /* file: smcc669.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) * Copyright (C) 1997 by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) * Digital Equipment Corporation, Maynard, Massachusetts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) * All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) * This software is furnished under a license and may be used and copied
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) * only in accordance of the terms of such license and with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) * inclusion of the above copyright notice. This software or any other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) * copies thereof may not be provided or otherwise made available to any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) * other person. No title to and ownership of the software is hereby
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) * transferred.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) * The information in this software is subject to change without notice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) * and should not be construed as a commitment by digital equipment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) * corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) * Digital assumes no responsibility for the use or reliability of its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) * software on equipment which is not supplied by digital.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) *++
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) * FACILITY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) * Alpha SRM Console Firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) * MODULE DESCRIPTION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) * SMC37c669 Super I/O controller configuration routines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) * AUTHORS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) * Eric Rasmussen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) * CREATION DATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) * 28-Jan-1997
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) * MODIFICATION HISTORY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) * er 01-May-1997 Fixed pointer conversion errors in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) * SMC37c669_get_device_config().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) * er 28-Jan-1997 Initial version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) *--
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) #ifndef TRUE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) #define TRUE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) #ifndef FALSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) #define FALSE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) #define wb( _x_, _y_ ) outb( _y_, (unsigned int)((unsigned long)_x_) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) #define rb( _x_ ) inb( (unsigned int)((unsigned long)_x_) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) ** Local storage for device configuration information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) ** Since the SMC37c669 does not provide an explicit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) ** mechanism for enabling/disabling individual device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) ** functions, other than unmapping the device, local
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) ** storage for device configuration information is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) ** allocated here for use in implementing our own
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) ** function enable/disable scheme.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) static struct DEVICE_CONFIG {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) unsigned int port1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) unsigned int port2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) int drq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) } local_config [NUM_FUNCS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) ** List of all possible addresses for the Super I/O chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) static unsigned long SMC37c669_Addresses[] __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) 0x3F0UL, /* Primary address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) 0x370UL, /* Secondary address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) 0UL /* End of list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) ** Global Pointer to the Super I/O device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) static SMC37c669_CONFIG_REGS *SMC37c669 __initdata = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) ** IRQ Translation Table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) ** The IRQ translation table is a list of SMC37c669 device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) ** and standard ISA IRQs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) static SMC37c669_IRQ_TRANSLATION_ENTRY *SMC37c669_irq_table __initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) ** The following definition is for the default IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) ** translation table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) static SMC37c669_IRQ_TRANSLATION_ENTRY SMC37c669_default_irq_table[]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) { SMC37c669_DEVICE_IRQ_A, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) { SMC37c669_DEVICE_IRQ_B, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) { SMC37c669_DEVICE_IRQ_C, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) { SMC37c669_DEVICE_IRQ_D, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) { SMC37c669_DEVICE_IRQ_E, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) { SMC37c669_DEVICE_IRQ_F, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) { SMC37c669_DEVICE_IRQ_H, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) { -1, -1 } /* End of table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) ** The following definition is for the MONET (XP1000) IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) ** translation table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) static SMC37c669_IRQ_TRANSLATION_ENTRY SMC37c669_monet_irq_table[]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) { SMC37c669_DEVICE_IRQ_A, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) { SMC37c669_DEVICE_IRQ_B, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) { SMC37c669_DEVICE_IRQ_C, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) { SMC37c669_DEVICE_IRQ_D, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) { SMC37c669_DEVICE_IRQ_E, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) { SMC37c669_DEVICE_IRQ_F, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) { SMC37c669_DEVICE_IRQ_H, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) { -1, -1 } /* End of table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) static SMC37c669_IRQ_TRANSLATION_ENTRY *SMC37c669_irq_tables[] __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) SMC37c669_default_irq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) SMC37c669_monet_irq_table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) ** DRQ Translation Table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) ** The DRQ translation table is a list of SMC37c669 device and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) ** ISA DMA channels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) static SMC37c669_DRQ_TRANSLATION_ENTRY *SMC37c669_drq_table __initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) ** The following definition is the default DRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) ** translation table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) static SMC37c669_DRQ_TRANSLATION_ENTRY SMC37c669_default_drq_table[]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) __initdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) { SMC37c669_DEVICE_DRQ_A, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) { SMC37c669_DEVICE_DRQ_B, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) { SMC37c669_DEVICE_DRQ_C, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) { -1, -1 } /* End of table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) ** Local Function Prototype Declarations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) static unsigned int SMC37c669_is_device_enabled(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) unsigned int func
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) static unsigned int SMC37c669_get_device_config(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) unsigned int func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) int *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) int *irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) int *drq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) static void SMC37c669_config_mode(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) unsigned int enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) static unsigned char SMC37c669_read_config(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) unsigned char index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) static void SMC37c669_write_config(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) unsigned char index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) unsigned char data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) static void SMC37c669_init_local_config( void );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) static struct DEVICE_CONFIG *SMC37c669_get_config(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) unsigned int func
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) static int SMC37c669_xlate_irq(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) int irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) static int SMC37c669_xlate_drq(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) int drq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) static __cacheline_aligned DEFINE_SPINLOCK(smc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) **++
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) ** FUNCTIONAL DESCRIPTION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) ** This function detects the presence of an SMC37c669 Super I/O
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) ** controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) ** FORMAL PARAMETERS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) ** None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) ** RETURN VALUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) ** Returns a pointer to the device if found, otherwise,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) ** the NULL pointer is returned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) ** SIDE EFFECTS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) ** None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) **--
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) SMC37c669_CONFIG_REGS * __init SMC37c669_detect( int index )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) SMC37c669_DEVICE_ID_REGISTER id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) for ( i = 0; SMC37c669_Addresses[i] != 0; i++ ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) ** Initialize the device pointer even though we don't yet know if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) ** the controller is at this address. The support functions access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) ** the controller through this device pointer so we need to set it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) ** even when we are looking ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) SMC37c669 = ( SMC37c669_CONFIG_REGS * )SMC37c669_Addresses[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) ** Enter configuration mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) SMC37c669_config_mode( TRUE );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) ** Read the device id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) id.as_uchar = SMC37c669_read_config( SMC37c669_DEVICE_ID_INDEX );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) ** Exit configuration mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) SMC37c669_config_mode( FALSE );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) ** Does the device id match? If so, assume we have found an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) ** SMC37c669 controller at this address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) if ( id.by_field.device_id == SMC37c669_DEVICE_ID ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) ** Initialize the IRQ and DRQ translation tables.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) SMC37c669_irq_table = SMC37c669_irq_tables[ index ];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) SMC37c669_drq_table = SMC37c669_default_drq_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) ** erfix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) ** If the platform can't use the IRQ and DRQ defaults set up in this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) ** file, it should call a platform-specific external routine at this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) ** point to reset the IRQ and DRQ translation table pointers to point
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) ** at the appropriate tables for the platform. If the defaults are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) ** acceptable, then the external routine should do nothing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) ** Put the chip back into configuration mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) SMC37c669_config_mode( TRUE );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) ** Initialize local storage for configuration information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) SMC37c669_init_local_config( );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) ** Exit configuration mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) SMC37c669_config_mode( FALSE );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) ** SMC37c669 controller found, break out of search loop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) ** Otherwise, we did not find an SMC37c669 controller at this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) ** address so set the device pointer to NULL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) SMC37c669 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) return SMC37c669;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) **++
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) ** FUNCTIONAL DESCRIPTION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) ** This function enables an SMC37c669 device function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) ** FORMAL PARAMETERS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) ** func:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) ** Which device function to enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) ** RETURN VALUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) ** Returns TRUE is the device function was enabled, otherwise, FALSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) ** SIDE EFFECTS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) ** {@description or none@}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) ** DESIGN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) ** Enabling a device function in the SMC37c669 controller involves
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) ** setting all of its mappings (port, irq, drq ...). A local
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) ** "shadow" copy of the device configuration is kept so we can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) ** just set each mapping to what the local copy says.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) ** This function ALWAYS updates the local shadow configuration of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) ** the device function being enabled, even if the device is always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) ** enabled. To avoid replication of code, functions such as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) ** configure_device set up the local copy and then call this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) ** function to the update the real device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) **--
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) unsigned int __init SMC37c669_enable_device ( unsigned int func )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) unsigned int ret_val = FALSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) ** Put the device into configuration mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) SMC37c669_config_mode( TRUE );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) switch ( func ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) case SERIAL_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) SMC37c669_SERIAL_BASE_ADDRESS_REGISTER base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) SMC37c669_SERIAL_IRQ_REGISTER irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) ** Enable the serial 1 IRQ mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) irq.as_uchar =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) SMC37c669_read_config( SMC37c669_SERIAL_IRQ_INDEX );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) irq.by_field.uart1_irq =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) SMC37c669_RAW_DEVICE_IRQ(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) SMC37c669_xlate_irq( local_config[ func ].irq )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) SMC37c669_write_config( SMC37c669_SERIAL_IRQ_INDEX, irq.as_uchar );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) ** Enable the serial 1 port base address mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) base_addr.as_uchar = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) base_addr.by_field.addr9_3 = local_config[ func ].port1 >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) SMC37c669_write_config(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) SMC37c669_SERIAL0_BASE_ADDRESS_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) base_addr.as_uchar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) ret_val = TRUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) case SERIAL_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) SMC37c669_SERIAL_BASE_ADDRESS_REGISTER base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) SMC37c669_SERIAL_IRQ_REGISTER irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) ** Enable the serial 2 IRQ mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) irq.as_uchar =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) SMC37c669_read_config( SMC37c669_SERIAL_IRQ_INDEX );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) irq.by_field.uart2_irq =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) SMC37c669_RAW_DEVICE_IRQ(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) SMC37c669_xlate_irq( local_config[ func ].irq )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) SMC37c669_write_config( SMC37c669_SERIAL_IRQ_INDEX, irq.as_uchar );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) ** Enable the serial 2 port base address mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) base_addr.as_uchar = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) base_addr.by_field.addr9_3 = local_config[ func ].port1 >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) SMC37c669_write_config(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) SMC37c669_SERIAL1_BASE_ADDRESS_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) base_addr.as_uchar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) ret_val = TRUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) case PARALLEL_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) SMC37c669_PARALLEL_BASE_ADDRESS_REGISTER base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) SMC37c669_PARALLEL_FDC_IRQ_REGISTER irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) SMC37c669_PARALLEL_FDC_DRQ_REGISTER drq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) ** Enable the parallel port DMA channel mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) drq.as_uchar =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) SMC37c669_read_config( SMC37c669_PARALLEL_FDC_DRQ_INDEX );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) drq.by_field.ppt_drq =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) SMC37c669_RAW_DEVICE_DRQ(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) SMC37c669_xlate_drq( local_config[ func ].drq )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) SMC37c669_write_config(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) SMC37c669_PARALLEL_FDC_DRQ_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) drq.as_uchar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) ** Enable the parallel port IRQ mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) irq.as_uchar =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) SMC37c669_read_config( SMC37c669_PARALLEL_FDC_IRQ_INDEX );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) irq.by_field.ppt_irq =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) SMC37c669_RAW_DEVICE_IRQ(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) SMC37c669_xlate_irq( local_config[ func ].irq )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) SMC37c669_write_config(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) SMC37c669_PARALLEL_FDC_IRQ_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) irq.as_uchar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) ** Enable the parallel port base address mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) base_addr.as_uchar = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) base_addr.by_field.addr9_2 = local_config[ func ].port1 >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) SMC37c669_write_config(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) SMC37c669_PARALLEL0_BASE_ADDRESS_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) base_addr.as_uchar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) ret_val = TRUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) case FLOPPY_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) SMC37c669_FDC_BASE_ADDRESS_REGISTER base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) SMC37c669_PARALLEL_FDC_IRQ_REGISTER irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) SMC37c669_PARALLEL_FDC_DRQ_REGISTER drq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) ** Enable the floppy controller DMA channel mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) drq.as_uchar =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) SMC37c669_read_config( SMC37c669_PARALLEL_FDC_DRQ_INDEX );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) drq.by_field.fdc_drq =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) SMC37c669_RAW_DEVICE_DRQ(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) SMC37c669_xlate_drq( local_config[ func ].drq )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) SMC37c669_write_config(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) SMC37c669_PARALLEL_FDC_DRQ_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) drq.as_uchar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) ** Enable the floppy controller IRQ mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) irq.as_uchar =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) SMC37c669_read_config( SMC37c669_PARALLEL_FDC_IRQ_INDEX );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) irq.by_field.fdc_irq =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) SMC37c669_RAW_DEVICE_IRQ(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) SMC37c669_xlate_irq( local_config[ func ].irq )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) SMC37c669_write_config(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) SMC37c669_PARALLEL_FDC_IRQ_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) irq.as_uchar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) ** Enable the floppy controller base address mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) base_addr.as_uchar = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) base_addr.by_field.addr9_4 = local_config[ func ].port1 >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) SMC37c669_write_config(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) SMC37c669_FDC_BASE_ADDRESS_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) base_addr.as_uchar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) ret_val = TRUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) case IDE_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) SMC37c669_IDE_ADDRESS_REGISTER ide_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) ** Enable the IDE alternate status base address mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) ide_addr.as_uchar = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) ide_addr.by_field.addr9_4 = local_config[ func ].port2 >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) SMC37c669_write_config(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) SMC37c669_IDE_ALTERNATE_ADDRESS_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) ide_addr.as_uchar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) ** Enable the IDE controller base address mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) ide_addr.as_uchar = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) ide_addr.by_field.addr9_4 = local_config[ func ].port1 >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) SMC37c669_write_config(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) SMC37c669_IDE_BASE_ADDRESS_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) ide_addr.as_uchar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) ret_val = TRUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) ** Exit configuration mode and return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) SMC37c669_config_mode( FALSE );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) return ret_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) **++
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) ** FUNCTIONAL DESCRIPTION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) ** This function disables a device function within the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) ** SMC37c669 Super I/O controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) ** FORMAL PARAMETERS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) ** func:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) ** Which function to disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) ** RETURN VALUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) ** Return TRUE if the device function was disabled, otherwise, FALSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) ** SIDE EFFECTS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) ** {@description or none@}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) ** DESIGN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) ** Disabling a function in the SMC37c669 device involves
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) ** disabling all the function's mappings (port, irq, drq ...).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) ** A shadow copy of the device configuration is maintained
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) ** in local storage so we won't worry aboving saving the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) ** current configuration information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) **--
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) unsigned int __init SMC37c669_disable_device ( unsigned int func )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) unsigned int ret_val = FALSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) ** Put the device into configuration mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) SMC37c669_config_mode( TRUE );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) switch ( func ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) case SERIAL_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) SMC37c669_SERIAL_BASE_ADDRESS_REGISTER base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) SMC37c669_SERIAL_IRQ_REGISTER irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) ** Disable the serial 1 IRQ mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) irq.as_uchar =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) SMC37c669_read_config( SMC37c669_SERIAL_IRQ_INDEX );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) irq.by_field.uart1_irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) SMC37c669_write_config( SMC37c669_SERIAL_IRQ_INDEX, irq.as_uchar );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) ** Disable the serial 1 port base address mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) base_addr.as_uchar = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) SMC37c669_write_config(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) SMC37c669_SERIAL0_BASE_ADDRESS_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) base_addr.as_uchar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) ret_val = TRUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) case SERIAL_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) SMC37c669_SERIAL_BASE_ADDRESS_REGISTER base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) SMC37c669_SERIAL_IRQ_REGISTER irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) ** Disable the serial 2 IRQ mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) irq.as_uchar =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) SMC37c669_read_config( SMC37c669_SERIAL_IRQ_INDEX );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) irq.by_field.uart2_irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) SMC37c669_write_config( SMC37c669_SERIAL_IRQ_INDEX, irq.as_uchar );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) ** Disable the serial 2 port base address mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) base_addr.as_uchar = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) SMC37c669_write_config(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) SMC37c669_SERIAL1_BASE_ADDRESS_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) base_addr.as_uchar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) ret_val = TRUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) case PARALLEL_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) SMC37c669_PARALLEL_BASE_ADDRESS_REGISTER base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) SMC37c669_PARALLEL_FDC_IRQ_REGISTER irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) SMC37c669_PARALLEL_FDC_DRQ_REGISTER drq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) ** Disable the parallel port DMA channel mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) drq.as_uchar =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) SMC37c669_read_config( SMC37c669_PARALLEL_FDC_DRQ_INDEX );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) drq.by_field.ppt_drq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) SMC37c669_write_config(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) SMC37c669_PARALLEL_FDC_DRQ_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) drq.as_uchar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) ** Disable the parallel port IRQ mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) irq.as_uchar =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) SMC37c669_read_config( SMC37c669_PARALLEL_FDC_IRQ_INDEX );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) irq.by_field.ppt_irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) SMC37c669_write_config(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) SMC37c669_PARALLEL_FDC_IRQ_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) irq.as_uchar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) ** Disable the parallel port base address mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) base_addr.as_uchar = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) SMC37c669_write_config(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) SMC37c669_PARALLEL0_BASE_ADDRESS_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) base_addr.as_uchar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) ret_val = TRUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) case FLOPPY_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) SMC37c669_FDC_BASE_ADDRESS_REGISTER base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) SMC37c669_PARALLEL_FDC_IRQ_REGISTER irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) SMC37c669_PARALLEL_FDC_DRQ_REGISTER drq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) ** Disable the floppy controller DMA channel mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) drq.as_uchar =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) SMC37c669_read_config( SMC37c669_PARALLEL_FDC_DRQ_INDEX );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) drq.by_field.fdc_drq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) SMC37c669_write_config(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) SMC37c669_PARALLEL_FDC_DRQ_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) drq.as_uchar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) ** Disable the floppy controller IRQ mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) irq.as_uchar =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) SMC37c669_read_config( SMC37c669_PARALLEL_FDC_IRQ_INDEX );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) irq.by_field.fdc_irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) SMC37c669_write_config(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) SMC37c669_PARALLEL_FDC_IRQ_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) irq.as_uchar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) ** Disable the floppy controller base address mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) base_addr.as_uchar = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) SMC37c669_write_config(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) SMC37c669_FDC_BASE_ADDRESS_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) base_addr.as_uchar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) ret_val = TRUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) case IDE_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) SMC37c669_IDE_ADDRESS_REGISTER ide_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) ** Disable the IDE alternate status base address mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) ide_addr.as_uchar = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) SMC37c669_write_config(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) SMC37c669_IDE_ALTERNATE_ADDRESS_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) ide_addr.as_uchar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) ** Disable the IDE controller base address mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) ide_addr.as_uchar = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) SMC37c669_write_config(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) SMC37c669_IDE_BASE_ADDRESS_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) ide_addr.as_uchar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) ret_val = TRUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) ** Exit configuration mode and return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) SMC37c669_config_mode( FALSE );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) return ret_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) **++
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) ** FUNCTIONAL DESCRIPTION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) ** This function configures a device function within the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) ** SMC37c669 Super I/O controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) ** FORMAL PARAMETERS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) ** func:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) ** Which device function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) ** port:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) ** I/O port for the function to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) ** irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) ** IRQ for the device function to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) ** drq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) ** DMA channel for the device function to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) ** RETURN VALUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) ** Returns TRUE if the device function was configured,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) ** otherwise, FALSE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) ** SIDE EFFECTS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) ** {@description or none@}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) ** DESIGN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) ** If this function returns TRUE, the local shadow copy of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) ** the configuration is also updated. If the device function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) ** is currently disabled, only the local shadow copy is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) ** updated and the actual device function will be updated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) ** if/when it is enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) **--
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) unsigned int __init SMC37c669_configure_device (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) unsigned int func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) int drq )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) struct DEVICE_CONFIG *cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) ** Check for a valid configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) if ( ( cp = SMC37c669_get_config ( func ) ) != NULL ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) ** Configuration is valid, update the local shadow copy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) if ( ( drq & ~0xFF ) == 0 ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) cp->drq = drq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) if ( ( irq & ~0xFF ) == 0 ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) cp->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) if ( ( port & ~0xFFFF ) == 0 ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) cp->port1 = port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) ** If the device function is enabled, update the actual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) ** device configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) if ( SMC37c669_is_device_enabled( func ) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) SMC37c669_enable_device( func );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) return TRUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) return FALSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) **++
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) ** FUNCTIONAL DESCRIPTION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) ** This function determines whether a device function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) ** within the SMC37c669 controller is enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) ** FORMAL PARAMETERS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) ** func:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) ** Which device function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) ** RETURN VALUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) ** Returns TRUE if the device function is enabled, otherwise, FALSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) ** SIDE EFFECTS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) ** {@description or none@}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) ** DESIGN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) ** To check whether a device is enabled we will only look at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) ** the port base address mapping. According to the SMC37c669
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) ** specification, all of the port base address mappings are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) ** disabled if the addr<9:8> (bits <7:6> of the register) are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) ** zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) **--
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) static unsigned int __init SMC37c669_is_device_enabled ( unsigned int func )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) unsigned char base_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) unsigned int dev_ok = FALSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) unsigned int ret_val = FALSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) ** Enter configuration mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) SMC37c669_config_mode( TRUE );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) switch ( func ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) case SERIAL_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) base_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) SMC37c669_read_config( SMC37c669_SERIAL0_BASE_ADDRESS_INDEX );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) dev_ok = TRUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) case SERIAL_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) base_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) SMC37c669_read_config( SMC37c669_SERIAL1_BASE_ADDRESS_INDEX );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) dev_ok = TRUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) case PARALLEL_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) base_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) SMC37c669_read_config( SMC37c669_PARALLEL0_BASE_ADDRESS_INDEX );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) dev_ok = TRUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) case FLOPPY_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) base_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) SMC37c669_read_config( SMC37c669_FDC_BASE_ADDRESS_INDEX );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) dev_ok = TRUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) case IDE_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) base_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) SMC37c669_read_config( SMC37c669_IDE_BASE_ADDRESS_INDEX );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) dev_ok = TRUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) ** If we have a valid device, check base_addr<7:6> to see if the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) ** device is enabled (mapped).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) if ( ( dev_ok ) && ( ( base_addr & 0xC0 ) != 0 ) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) ** The mapping is not disabled, so assume that the function is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) ** enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) ret_val = TRUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) ** Exit configuration mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) SMC37c669_config_mode( FALSE );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) return ret_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) **++
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) ** FUNCTIONAL DESCRIPTION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) ** This function retrieves the configuration information of a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) ** device function within the SMC37c699 Super I/O controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) ** FORMAL PARAMETERS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) ** func:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) ** Which device function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) ** port:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) ** I/O port returned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) ** irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) ** IRQ returned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) ** drq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) ** DMA channel returned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) ** RETURN VALUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) ** Returns TRUE if the device configuration was successfully
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) ** retrieved, otherwise, FALSE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) ** SIDE EFFECTS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) ** The data pointed to by the port, irq, and drq parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) ** my be modified even if the configuration is not successfully
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) ** retrieved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) ** DESIGN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) ** The device configuration is fetched from the local shadow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) ** copy. Any unused parameters will be set to -1. Any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) ** parameter which is not desired can specify the NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) ** pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) **--
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) static unsigned int __init SMC37c669_get_device_config (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) unsigned int func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) int *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) int *irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) int *drq )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) struct DEVICE_CONFIG *cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) unsigned int ret_val = FALSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) ** Check for a valid device configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) if ( ( cp = SMC37c669_get_config( func ) ) != NULL ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) if ( drq != NULL ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) *drq = cp->drq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) ret_val = TRUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) if ( irq != NULL ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) *irq = cp->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) ret_val = TRUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) if ( port != NULL ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) *port = cp->port1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) ret_val = TRUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) return ret_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) **++
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) ** FUNCTIONAL DESCRIPTION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) ** This function displays the current state of the SMC37c699
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) ** Super I/O controller's device functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) ** FORMAL PARAMETERS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) ** None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) ** RETURN VALUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) ** None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) ** SIDE EFFECTS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) ** None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) **--
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) void __init SMC37c669_display_device_info ( void )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) if ( SMC37c669_is_device_enabled( SERIAL_0 ) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) printk( " Serial 0: Enabled [ Port 0x%x, IRQ %d ]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) local_config[ SERIAL_0 ].port1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) local_config[ SERIAL_0 ].irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) printk( " Serial 0: Disabled\n" );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) if ( SMC37c669_is_device_enabled( SERIAL_1 ) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) printk( " Serial 1: Enabled [ Port 0x%x, IRQ %d ]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) local_config[ SERIAL_1 ].port1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) local_config[ SERIAL_1 ].irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) printk( " Serial 1: Disabled\n" );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) if ( SMC37c669_is_device_enabled( PARALLEL_0 ) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) printk( " Parallel: Enabled [ Port 0x%x, IRQ %d/%d ]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) local_config[ PARALLEL_0 ].port1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) local_config[ PARALLEL_0 ].irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) local_config[ PARALLEL_0 ].drq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) printk( " Parallel: Disabled\n" );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) if ( SMC37c669_is_device_enabled( FLOPPY_0 ) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) printk( " Floppy Ctrl: Enabled [ Port 0x%x, IRQ %d/%d ]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) local_config[ FLOPPY_0 ].port1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) local_config[ FLOPPY_0 ].irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) local_config[ FLOPPY_0 ].drq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) printk( " Floppy Ctrl: Disabled\n" );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) if ( SMC37c669_is_device_enabled( IDE_0 ) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) printk( " IDE 0: Enabled [ Port 0x%x, IRQ %d ]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) local_config[ IDE_0 ].port1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) local_config[ IDE_0 ].irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) printk( " IDE 0: Disabled\n" );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) **++
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) ** FUNCTIONAL DESCRIPTION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) ** This function puts the SMC37c669 Super I/O controller into,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) ** and takes it out of, configuration mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) ** FORMAL PARAMETERS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) ** enable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) ** TRUE to enter configuration mode, FALSE to exit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) ** RETURN VALUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) ** None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) ** SIDE EFFECTS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) ** The SMC37c669 controller may be left in configuration mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) **--
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) static void __init SMC37c669_config_mode(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) unsigned int enable )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) if ( enable ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) ** To enter configuration mode, two writes in succession to the index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) ** port are required. If a write to another address or port occurs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) ** between these two writes, the chip does not enter configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) ** mode. Therefore, a spinlock is placed around the two writes to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) ** guarantee that they complete uninterrupted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) spin_lock(&smc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) wb( &SMC37c669->index_port, SMC37c669_CONFIG_ON_KEY );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) wb( &SMC37c669->index_port, SMC37c669_CONFIG_ON_KEY );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) spin_unlock(&smc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) wb( &SMC37c669->index_port, SMC37c669_CONFIG_OFF_KEY );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) **++
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) ** FUNCTIONAL DESCRIPTION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) ** This function reads an SMC37c669 Super I/O controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) ** configuration register. This function assumes that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) ** device is already in configuration mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) ** FORMAL PARAMETERS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) ** index:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) ** Index value of configuration register to read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) ** RETURN VALUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) ** Data read from configuration register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) ** SIDE EFFECTS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) ** None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) **--
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) static unsigned char __init SMC37c669_read_config(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) unsigned char index )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) wb(&SMC37c669->index_port, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) return rb(&SMC37c669->data_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) **++
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) ** FUNCTIONAL DESCRIPTION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) ** This function writes an SMC37c669 Super I/O controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) ** configuration register. This function assumes that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) ** device is already in configuration mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) ** FORMAL PARAMETERS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) ** index:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) ** Index of configuration register to write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) ** data:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) ** Data to be written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) ** RETURN VALUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) ** None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) ** SIDE EFFECTS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) ** None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) **--
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) static void __init SMC37c669_write_config(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) unsigned char index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) unsigned char data )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) wb( &SMC37c669->index_port, index );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) wb( &SMC37c669->data_port, data );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) **++
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) ** FUNCTIONAL DESCRIPTION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) ** This function initializes the local device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) ** configuration storage. This function assumes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) ** that the device is already in configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) ** mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) ** FORMAL PARAMETERS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) ** None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) ** RETURN VALUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) ** None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) ** SIDE EFFECTS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) ** Local storage for device configuration information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) ** is initialized.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) **--
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) static void __init SMC37c669_init_local_config ( void )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) SMC37c669_SERIAL_BASE_ADDRESS_REGISTER uart_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) SMC37c669_SERIAL_IRQ_REGISTER uart_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) SMC37c669_PARALLEL_BASE_ADDRESS_REGISTER ppt_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) SMC37c669_PARALLEL_FDC_IRQ_REGISTER ppt_fdc_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) SMC37c669_PARALLEL_FDC_DRQ_REGISTER ppt_fdc_drqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) SMC37c669_FDC_BASE_ADDRESS_REGISTER fdc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) SMC37c669_IDE_ADDRESS_REGISTER ide_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) SMC37c669_IDE_ADDRESS_REGISTER ide_alt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) ** Get serial port 1 base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) uart_base.as_uchar =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) SMC37c669_read_config( SMC37c669_SERIAL0_BASE_ADDRESS_INDEX );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) ** Get IRQs for serial ports 1 & 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) uart_irqs.as_uchar =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) SMC37c669_read_config( SMC37c669_SERIAL_IRQ_INDEX );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) ** Store local configuration information for serial port 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) local_config[SERIAL_0].port1 = uart_base.by_field.addr9_3 << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) local_config[SERIAL_0].irq =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) SMC37c669_xlate_irq(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) SMC37c669_DEVICE_IRQ( uart_irqs.by_field.uart1_irq )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) ** Get serial port 2 base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) uart_base.as_uchar =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) SMC37c669_read_config( SMC37c669_SERIAL1_BASE_ADDRESS_INDEX );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) ** Store local configuration information for serial port 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) local_config[SERIAL_1].port1 = uart_base.by_field.addr9_3 << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) local_config[SERIAL_1].irq =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) SMC37c669_xlate_irq(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) SMC37c669_DEVICE_IRQ( uart_irqs.by_field.uart2_irq )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) ** Get parallel port base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) ppt_base.as_uchar =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) SMC37c669_read_config( SMC37c669_PARALLEL0_BASE_ADDRESS_INDEX );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) ** Get IRQs for parallel port and floppy controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) ppt_fdc_irqs.as_uchar =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) SMC37c669_read_config( SMC37c669_PARALLEL_FDC_IRQ_INDEX );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) ** Get DRQs for parallel port and floppy controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) ppt_fdc_drqs.as_uchar =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) SMC37c669_read_config( SMC37c669_PARALLEL_FDC_DRQ_INDEX );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) ** Store local configuration information for parallel port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) local_config[PARALLEL_0].port1 = ppt_base.by_field.addr9_2 << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) local_config[PARALLEL_0].irq =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) SMC37c669_xlate_irq(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) SMC37c669_DEVICE_IRQ( ppt_fdc_irqs.by_field.ppt_irq )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) local_config[PARALLEL_0].drq =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) SMC37c669_xlate_drq(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) SMC37c669_DEVICE_DRQ( ppt_fdc_drqs.by_field.ppt_drq )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) ** Get floppy controller base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) fdc_base.as_uchar =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) SMC37c669_read_config( SMC37c669_FDC_BASE_ADDRESS_INDEX );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) ** Store local configuration information for floppy controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) local_config[FLOPPY_0].port1 = fdc_base.by_field.addr9_4 << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) local_config[FLOPPY_0].irq =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) SMC37c669_xlate_irq(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) SMC37c669_DEVICE_IRQ( ppt_fdc_irqs.by_field.fdc_irq )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) local_config[FLOPPY_0].drq =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) SMC37c669_xlate_drq(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) SMC37c669_DEVICE_DRQ( ppt_fdc_drqs.by_field.fdc_drq )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) ** Get IDE controller base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) ide_base.as_uchar =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) SMC37c669_read_config( SMC37c669_IDE_BASE_ADDRESS_INDEX );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) ** Get IDE alternate status base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) ide_alt.as_uchar =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) SMC37c669_read_config( SMC37c669_IDE_ALTERNATE_ADDRESS_INDEX );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) ** Store local configuration information for IDE controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) local_config[IDE_0].port1 = ide_base.by_field.addr9_4 << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) local_config[IDE_0].port2 = ide_alt.by_field.addr9_4 << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) local_config[IDE_0].irq = 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) **++
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) ** FUNCTIONAL DESCRIPTION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) ** This function returns a pointer to the local shadow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) ** configuration of the requested device function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) ** FORMAL PARAMETERS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) ** func:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) ** Which device function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) ** RETURN VALUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) ** Returns a pointer to the DEVICE_CONFIG structure for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) ** requested function, otherwise, NULL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) ** SIDE EFFECTS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) ** {@description or none@}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) **--
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) static struct DEVICE_CONFIG * __init SMC37c669_get_config( unsigned int func )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) struct DEVICE_CONFIG *cp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) switch ( func ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) case SERIAL_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) cp = &local_config[ SERIAL_0 ];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) case SERIAL_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) cp = &local_config[ SERIAL_1 ];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) case PARALLEL_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) cp = &local_config[ PARALLEL_0 ];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) case FLOPPY_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) cp = &local_config[ FLOPPY_0 ];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) case IDE_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) cp = &local_config[ IDE_0 ];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) return cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) **++
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) ** FUNCTIONAL DESCRIPTION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) ** This function translates IRQs back and forth between ISA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) ** IRQs and SMC37c669 device IRQs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) ** FORMAL PARAMETERS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) ** irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) ** The IRQ to translate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) ** RETURN VALUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) ** Returns the translated IRQ, otherwise, returns -1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) ** SIDE EFFECTS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) ** {@description or none@}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) **--
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) static int __init SMC37c669_xlate_irq ( int irq )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) int i, translated_irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) if ( SMC37c669_IS_DEVICE_IRQ( irq ) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) ** We are translating a device IRQ to an ISA IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) for ( i = 0; ( SMC37c669_irq_table[i].device_irq != -1 ) || ( SMC37c669_irq_table[i].isa_irq != -1 ); i++ ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) if ( irq == SMC37c669_irq_table[i].device_irq ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) translated_irq = SMC37c669_irq_table[i].isa_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) ** We are translating an ISA IRQ to a device IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) for ( i = 0; ( SMC37c669_irq_table[i].isa_irq != -1 ) || ( SMC37c669_irq_table[i].device_irq != -1 ); i++ ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) if ( irq == SMC37c669_irq_table[i].isa_irq ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) translated_irq = SMC37c669_irq_table[i].device_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) return translated_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) **++
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) ** FUNCTIONAL DESCRIPTION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) ** This function translates DMA channels back and forth between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) ** ISA DMA channels and SMC37c669 device DMA channels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) ** FORMAL PARAMETERS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) ** drq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) ** The DMA channel to translate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) ** RETURN VALUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) ** Returns the translated DMA channel, otherwise, returns -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) ** SIDE EFFECTS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) ** {@description or none@}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) **--
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) static int __init SMC37c669_xlate_drq ( int drq )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) int i, translated_drq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) if ( SMC37c669_IS_DEVICE_DRQ( drq ) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) ** We are translating a device DMA channel to an ISA DMA channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) for ( i = 0; ( SMC37c669_drq_table[i].device_drq != -1 ) || ( SMC37c669_drq_table[i].isa_drq != -1 ); i++ ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) if ( drq == SMC37c669_drq_table[i].device_drq ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) translated_drq = SMC37c669_drq_table[i].isa_drq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) ** We are translating an ISA DMA channel to a device DMA channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) for ( i = 0; ( SMC37c669_drq_table[i].isa_drq != -1 ) || ( SMC37c669_drq_table[i].device_drq != -1 ); i++ ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) if ( drq == SMC37c669_drq_table[i].isa_drq ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) translated_drq = SMC37c669_drq_table[i].device_drq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) return translated_drq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) int __init smcc669_init ( void )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) struct INODE *ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) allocinode( smc_ddb.name, 1, &ip );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) ip->dva = &smc_ddb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) ip->attr = ATTR$M_WRITE | ATTR$M_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) ip->len[0] = 0x30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) ip->misc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) INODE_UNLOCK( ip );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) return msg_success;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) int __init smcc669_open( struct FILE *fp, char *info, char *next, char *mode )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) struct INODE *ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) ** Allow multiple readers but only one writer. ip->misc keeps track
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) ** of the number of writers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) ip = fp->ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) INODE_LOCK( ip );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) if ( fp->mode & ATTR$M_WRITE ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) if ( ip->misc ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) INODE_UNLOCK( ip );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) return msg_failure; /* too many writers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) ip->misc++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) ** Treat the information field as a byte offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) *fp->offset = xtoi( info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) INODE_UNLOCK( ip );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) return msg_success;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) int __init smcc669_close( struct FILE *fp )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) struct INODE *ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) ip = fp->ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) if ( fp->mode & ATTR$M_WRITE ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) INODE_LOCK( ip );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) ip->misc--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) INODE_UNLOCK( ip );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) return msg_success;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) int __init smcc669_read( struct FILE *fp, int size, int number, unsigned char *buf )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) int length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) int nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) struct INODE *ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) ** Always access a byte at a time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) ip = fp->ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) length = size * number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) nbytes = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) SMC37c669_config_mode( TRUE );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) for ( i = 0; i < length; i++ ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) if ( !inrange( *fp->offset, 0, ip->len[0] ) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) *buf++ = SMC37c669_read_config( *fp->offset );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) *fp->offset += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) nbytes++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) SMC37c669_config_mode( FALSE );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) return nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) int __init smcc669_write( struct FILE *fp, int size, int number, unsigned char *buf )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) int length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) int nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) struct INODE *ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) ** Always access a byte at a time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) ip = fp->ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) length = size * number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) nbytes = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) SMC37c669_config_mode( TRUE );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) for ( i = 0; i < length; i++ ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) if ( !inrange( *fp->offset, 0, ip->len[0] ) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) SMC37c669_write_config( *fp->offset, *buf );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) *fp->offset += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) buf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) nbytes++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) SMC37c669_config_mode( FALSE );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) return nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) SMC37c669_dump_registers(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) for (i = 0; i <= 0x29; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) printk("-- CR%02x : %02x\n", i, SMC37c669_read_config(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) /*+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) * ============================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) * = SMC_init - SMC37c669 Super I/O controller initialization =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) * ============================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) * OVERVIEW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) * This routine configures and enables device functions on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) * SMC37c669 Super I/O controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) * FORM OF CALL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) * SMC_init( );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) * RETURNS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) * Nothing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) * ARGUMENTS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) * None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) * SIDE EFFECTS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) * None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) void __init SMC669_Init ( int index )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) SMC37c669_CONFIG_REGS *SMC_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) if ( ( SMC_base = SMC37c669_detect( index ) ) != NULL ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) #if SMC_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) SMC37c669_config_mode( TRUE );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) SMC37c669_dump_registers( );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) SMC37c669_config_mode( FALSE );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) SMC37c669_display_device_info( );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) SMC37c669_disable_device( SERIAL_0 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) SMC37c669_configure_device(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) SERIAL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) COM1_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) COM1_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) SMC37c669_enable_device( SERIAL_0 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) SMC37c669_disable_device( SERIAL_1 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) SMC37c669_configure_device(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) SERIAL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) COM2_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) COM2_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) SMC37c669_enable_device( SERIAL_1 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) SMC37c669_disable_device( PARALLEL_0 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) SMC37c669_configure_device(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) PARALLEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) PARP_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) PARP_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) PARP_DRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) SMC37c669_enable_device( PARALLEL_0 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) SMC37c669_disable_device( FLOPPY_0 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) SMC37c669_configure_device(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) FLOPPY_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) FDC_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) FDC_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) FDC_DRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) SMC37c669_enable_device( FLOPPY_0 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) /* Wake up sometimes forgotten floppy, especially on DP264. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) outb(0xc, 0x3f2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) SMC37c669_disable_device( IDE_0 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) #if SMC_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) SMC37c669_config_mode( TRUE );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) SMC37c669_dump_registers( );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) SMC37c669_config_mode( FALSE );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) SMC37c669_display_device_info( );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) printk( "SMC37c669 Super I/O Controller found @ 0x%p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) SMC_base );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) #if SMC_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) printk( "No SMC37c669 Super I/O Controller found\n" );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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