^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/alpha/kernel/pci_impl.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * This file contains declarations and inline functions for interfacing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * with the PCI initialization routines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) struct pci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) struct pci_controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) struct pci_iommu_arena;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * We can't just blindly use 64K for machines with EISA busses; they
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * may also have PCI-PCI bridges present, and then we'd configure the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * bridge incorrectly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Also, we start at 0x8000 or 0x9000, in hopes to get all devices'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * IO space areas allocated *before* 0xC000; this is because certain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * BIOSes (Millennium for one) use PCI Config space "mechanism #2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * accesses to probe the bus. If a device's registers appear at 0xC000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * it may see an INx/OUTx at that address during BIOS emulation of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * VGA BIOS, and some cards, notably Adaptec 2940UW, take mortal offense.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define EISA_DEFAULT_IO_BASE 0x9000 /* start above 8th slot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DEFAULT_IO_BASE 0x8000 /* start at 8th slot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * We try to make the DEFAULT_MEM_BASE addresses *always* have more than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * a single bit set. This is so that devices like the broken Myrinet card
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * will always have a PCI memory address that will never match a IDSEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * address in PCI Config space, which can cause problems with early rev cards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * An XL is AVANTI (APECS) family, *but* it has only 27 bits of ISA address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * that get passed through the PCI<->ISA bridge chip. Although this causes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * us to set the PCI->Mem window bases lower than normal, we still allocate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * PCI bus devices' memory addresses *below* the low DMA mapping window,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * and hope they fit below 64Mb (to avoid conflicts), and so that they can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * be accessed via SPARSE space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * We accept the risk that a broken Myrinet card will be put into a true XL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * and thus can more easily run into the problem described below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define XL_DEFAULT_MEM_BASE ((16+2)*1024*1024) /* 16M to 64M-1 is avail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * APECS and LCA have only 34 bits for physical addresses, thus limiting PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * bus memory addresses for SPARSE access to be less than 128Mb.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define APECS_AND_LCA_DEFAULT_MEM_BASE ((16+2)*1024*1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * Because MCPCIA and T2 core logic support more bits for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * physical addresses, they should allow an expanded range of SPARSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * memory addresses. However, we do not use them all, in order to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * avoid the HAE manipulation that would be needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MCPCIA_DEFAULT_MEM_BASE ((32+2)*1024*1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define T2_DEFAULT_MEM_BASE ((16+1)*1024*1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * Because CIA and PYXIS have more bits for physical addresses,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * they support an expanded range of SPARSE memory addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DEFAULT_MEM_BASE ((128+16)*1024*1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* ??? Experimenting with no HAE for CIA. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CIA_DEFAULT_MEM_BASE ((32+2)*1024*1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define IRONGATE_DEFAULT_MEM_BASE ((256*8-16)*1024*1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define DEFAULT_AGP_APER_SIZE (64*1024*1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * A small note about bridges and interrupts. The DECchip 21050 (and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * later) adheres to the PCI-PCI bridge specification. This says that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * the interrupts on the other side of a bridge are swizzled in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * following manner:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * Dev Interrupt Interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * Pin on Pin on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * Device Connector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * 4 A A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * B B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * C C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * D D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * 5 A B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * B C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * C D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * D A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * 6 A C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * B D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * C A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * D B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * 7 A D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * B A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * C B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * D C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * Where A = pin 1, B = pin 2 and so on and pin=0 = default = A.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * Thus, each swizzle is ((pin-1) + (device#-4)) % 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * pci_swizzle_interrupt_pin() swizzles for exactly one bridge. The routine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * pci_common_swizzle() handles multiple bridges. But there are a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * couple boards that do strange things.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* The following macro is used to implement the table-based irq mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) function for all single-bus Alphas. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define COMMON_TABLE_LOOKUP \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) ({ long _ctl_ = -1; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (slot >= min_idsel && slot <= max_idsel && pin < irqs_per_slot) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) _ctl_ = irq_tab[slot - min_idsel][pin]; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) _ctl_; })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* A PCI IOMMU allocation arena. There are typically two of these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) regions per bus. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* ??? The 8400 has a 32-byte pte entry, and the entire table apparently
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) lives directly on the host bridge (no tlb?). We don't support this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) machine, but if we ever did, we'd need to parameterize all this quite
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) a bit further. Probably with per-bus operation tables. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct pci_iommu_arena
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct pci_controller *hose;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define IOMMU_INVALID_PTE 0x2 /* 32:63 bits MBZ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define IOMMU_RESERVED_PTE 0xface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) unsigned long *ptes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) dma_addr_t dma_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) unsigned int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) unsigned int next_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) unsigned int align_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #if defined(CONFIG_ALPHA_SRM) && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) (defined(CONFIG_ALPHA_CIA) || defined(CONFIG_ALPHA_LCA) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) defined(CONFIG_ALPHA_AVANTI))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) # define NEED_SRM_SAVE_RESTORE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) # undef NEED_SRM_SAVE_RESTORE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #if defined(CONFIG_ALPHA_GENERIC) || defined(NEED_SRM_SAVE_RESTORE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) # define ALPHA_RESTORE_SRM_SETUP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) # undef ALPHA_RESTORE_SRM_SETUP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #ifdef ALPHA_RESTORE_SRM_SETUP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) extern void pci_restore_srm_config(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define pci_restore_srm_config() do {} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* The hose list. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) extern struct pci_controller *hose_head, **hose_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) extern struct pci_controller *pci_isa_hose;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) extern unsigned long alpha_agpgart_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) extern void common_init_pci(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define common_swizzle pci_common_swizzle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) extern struct pci_controller *alloc_pci_controller(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) extern struct resource *alloc_resource(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) extern struct pci_iommu_arena *iommu_arena_new_node(int,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct pci_controller *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) dma_addr_t, unsigned long,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) unsigned long);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) extern struct pci_iommu_arena *iommu_arena_new(struct pci_controller *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) dma_addr_t, unsigned long,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) unsigned long);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) extern const char *const pci_io_names[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) extern const char *const pci_mem_names[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) extern const char pci_hae0_name[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) extern unsigned long size_for_memory(unsigned long max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) extern int iommu_reserve(struct pci_iommu_arena *, long, long);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) extern int iommu_release(struct pci_iommu_arena *, long, long);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) extern int iommu_bind(struct pci_iommu_arena *, long, long, struct page **);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) extern int iommu_unbind(struct pci_iommu_arena *, long, long);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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