^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/alpha/kernel/pci.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Extruded from code written by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Dave Rusling (david.rusling@reo.mts.dec.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * David Mosberger (davidm@cs.arizona.edu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* 2.3.x PCI/resources, 1999 Andrea Arcangeli <andrea@suse.de> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * PCI-PCI bridges cleanup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/memblock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/cache.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/syscalls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/machvec.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "proto.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "pci_impl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * Some string constants used by the various core logics.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) const char *const pci_io_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) "PCI IO bus 0", "PCI IO bus 1", "PCI IO bus 2", "PCI IO bus 3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) "PCI IO bus 4", "PCI IO bus 5", "PCI IO bus 6", "PCI IO bus 7"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) const char *const pci_mem_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) "PCI mem bus 0", "PCI mem bus 1", "PCI mem bus 2", "PCI mem bus 3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) "PCI mem bus 4", "PCI mem bus 5", "PCI mem bus 6", "PCI mem bus 7"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) const char pci_hae0_name[] = "HAE0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * If PCI_PROBE_ONLY in pci_flags is set, we don't change any PCI resource
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * assignments.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * The PCI controller list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct pci_controller *hose_head, **hose_tail = &hose_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct pci_controller *pci_isa_hose;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * Quirks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static void quirk_isa_bridge(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) dev->class = PCI_CLASS_BRIDGE_ISA << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82378, quirk_isa_bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static void quirk_cypress(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* The Notorious Cy82C693 chip. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* The generic legacy mode IDE fixup in drivers/pci/probe.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) doesn't work correctly with the Cypress IDE controller as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) it has non-standard register layout. Fix that. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) dev->resource[2].start = dev->resource[3].start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) dev->resource[2].end = dev->resource[3].end = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) dev->resource[2].flags = dev->resource[3].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (PCI_FUNC(dev->devfn) == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) dev->resource[0].start = 0x170;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) dev->resource[0].end = 0x177;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) dev->resource[1].start = 0x376;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) dev->resource[1].end = 0x376;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* The Cypress bridge responds on the PCI bus in the address range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) 0xffff0000-0xffffffff (conventional x86 BIOS ROM). There is no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) way to turn this off. The bridge also supports several extended
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) BIOS ranges (disabled after power-up), and some consoles do turn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) them on. So if we use a large direct-map window, or a large SG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) window, we must avoid the entire 0xfff00000-0xffffffff region. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (dev->class >> 8 == PCI_CLASS_BRIDGE_ISA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (__direct_map_base + __direct_map_size >= 0xfff00000UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) __direct_map_size = 0xfff00000UL - __direct_map_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct pci_controller *hose = dev->sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct pci_iommu_arena *pci = hose->sg_pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (pci && pci->dma_base + pci->size >= 0xfff00000UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) pci->size = 0xfff00000UL - pci->dma_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, quirk_cypress);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* Called for each device after PCI setup is done. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static void pcibios_fixup_final(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) unsigned int class = dev->class >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (class == PCI_CLASS_BRIDGE_ISA || class == PCI_CLASS_BRIDGE_EISA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) dev->dma_mask = MAX_ISA_DMA_ADDRESS - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) isa_bridge = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_final);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* Just declaring that the power-of-ten prefixes are actually the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) power-of-two ones doesn't make it true :) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define KB 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define MB (1024*KB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define GB (1024*MB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) resource_size_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) pcibios_align_resource(void *data, const struct resource *res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) resource_size_t size, resource_size_t align)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct pci_dev *dev = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct pci_controller *hose = dev->sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) unsigned long alignto;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) resource_size_t start = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (res->flags & IORESOURCE_IO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* Make sure we start at our min on all hoses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (start - hose->io_space->start < PCIBIOS_MIN_IO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) start = PCIBIOS_MIN_IO + hose->io_space->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * Put everything into 0x00-0xff region modulo 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (start & 0x300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) start = (start + 0x3ff) & ~0x3ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) else if (res->flags & IORESOURCE_MEM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* Make sure we start at our min on all hoses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (start - hose->mem_space->start < PCIBIOS_MIN_MEM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) start = PCIBIOS_MIN_MEM + hose->mem_space->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * The following holds at least for the Low Cost
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * Alpha implementation of the PCI interface:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * In sparse memory address space, the first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * octant (16MB) of every 128MB segment is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * aliased to the very first 16 MB of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * address space (i.e., it aliases the ISA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * memory address space). Thus, we try to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * avoid allocating PCI devices in that range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * Can be allocated in 2nd-7th octant only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * Devices that need more than 112MB of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * address space must be accessed through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * dense memory space only!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* Align to multiple of size of minimum base. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) alignto = max_t(resource_size_t, 0x1000, align);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) start = ALIGN(start, alignto);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (hose->sparse_mem_base && size <= 7 * 16*MB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (((start / (16*MB)) & 0x7) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) start &= ~(128*MB - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) start += 16*MB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) start = ALIGN(start, alignto);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (start/(128*MB) != (start + size - 1)/(128*MB)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) start &= ~(128*MB - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) start += (128 + 16)*MB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) start = ALIGN(start, alignto);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #undef KB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #undef MB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #undef GB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) pcibios_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (alpha_mv.init_pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) alpha_mv.init_pci();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) subsys_initcall(pcibios_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #ifdef ALPHA_RESTORE_SRM_SETUP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* Store PCI device configuration left by SRM here. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct pdev_srm_saved_conf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct pdev_srm_saved_conf *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static struct pdev_srm_saved_conf *srm_saved_configs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static void pdev_save_srm_config(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct pdev_srm_saved_conf *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static int printed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (!alpha_using_srm || pci_has_flag(PCI_PROBE_ONLY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (!printed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) printk(KERN_INFO "pci: enabling save/restore of SRM state\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) printed = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (!tmp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) printk(KERN_ERR "%s: kmalloc() failed!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) tmp->next = srm_saved_configs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) tmp->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) pci_save_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) srm_saved_configs = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) pci_restore_srm_config(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct pdev_srm_saved_conf *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* No need to restore if probed only. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (pci_has_flag(PCI_PROBE_ONLY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* Restore SRM config. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) for (tmp = srm_saved_configs; tmp; tmp = tmp->next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) pci_restore_state(tmp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define pdev_save_srm_config(dev) do {} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) void pcibios_fixup_bus(struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct pci_dev *dev = bus->self;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (pci_has_flag(PCI_PROBE_ONLY) && dev &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) pci_read_bridge_bases(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) list_for_each_entry(dev, &bus->devices, bus_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) pdev_save_srm_config(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * If we set up a device for bus mastering, we need to check the latency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * timer as certain firmware forgets to set it properly, as seen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * on SX164 and LX164 with SRM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) pcibios_set_master(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) u8 lat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (lat >= 16) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) printk("PCI: Setting latency timer of device %s to 64\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) pci_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) pcibios_claim_one_bus(struct pci_bus *b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct pci_bus *child_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) list_for_each_entry(dev, &b->devices, bus_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) for (i = 0; i < PCI_NUM_RESOURCES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct resource *r = &dev->resource[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (r->parent || !r->start || !r->flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (pci_has_flag(PCI_PROBE_ONLY) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) (r->flags & IORESOURCE_PCI_FIXED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (pci_claim_resource(dev, i) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) pci_claim_bridge_resource(dev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) list_for_each_entry(child_bus, &b->children, node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) pcibios_claim_one_bus(child_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) pcibios_claim_console_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct pci_bus *b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) list_for_each_entry(b, &pci_root_buses, node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) pcibios_claim_one_bus(b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) common_init_pci(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct pci_controller *hose;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct list_head resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct pci_host_bridge *bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct pci_bus *bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) int ret, next_busno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) int need_domain_info = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) u32 pci_mem_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) u32 sg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) unsigned long end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* Scan all of the recorded PCI controllers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) for (next_busno = 0, hose = hose_head; hose; hose = hose->next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) sg_base = hose->sg_pci ? hose->sg_pci->dma_base : ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* Adjust hose mem_space limit to prevent PCI allocations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) in the iommu windows. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) pci_mem_end = min((u32)__direct_map_base, sg_base) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) end = hose->mem_space->start + pci_mem_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (hose->mem_space->end > end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) hose->mem_space->end = end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) INIT_LIST_HEAD(&resources);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) pci_add_resource_offset(&resources, hose->io_space,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) hose->io_space->start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) pci_add_resource_offset(&resources, hose->mem_space,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) hose->mem_space->start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) bridge = pci_alloc_host_bridge(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (!bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) list_splice_init(&resources, &bridge->windows);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) bridge->dev.parent = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) bridge->sysdata = hose;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) bridge->busnr = next_busno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) bridge->ops = alpha_mv.pci_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) bridge->swizzle_irq = alpha_mv.pci_swizzle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) bridge->map_irq = alpha_mv.pci_map_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) ret = pci_scan_root_bus_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) pci_free_host_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) bus = hose->bus = bridge->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) hose->need_domain_info = need_domain_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) next_busno = bus->busn_res.end + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* Don't allow 8-bit bus number overflow inside the hose -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) reserve some space for bridges. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (next_busno > 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) next_busno = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) need_domain_info = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) pcibios_claim_console_setup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) pci_assign_unassigned_resources();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) for (hose = hose_head; hose; hose = hose->next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) bus = hose->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) pci_bus_add_devices(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct pci_controller * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) alloc_pci_controller(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct pci_controller *hose;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) hose = memblock_alloc(sizeof(*hose), SMP_CACHE_BYTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (!hose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) panic("%s: Failed to allocate %zu bytes\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) sizeof(*hose));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) *hose_tail = hose;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) hose_tail = &hose->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) return hose;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct resource * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) alloc_resource(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) void *ptr = memblock_alloc(sizeof(struct resource), SMP_CACHE_BYTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (!ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) panic("%s: Failed to allocate %zu bytes\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) sizeof(struct resource));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* Provide information on locations of various I/O regions in physical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) memory. Do this on a per-card basis so that we choose the right hose. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) SYSCALL_DEFINE3(pciconfig_iobase, long, which, unsigned long, bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) unsigned long, dfn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) struct pci_controller *hose;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /* from hose or from bus.devfn */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (which & IOBASE_FROM_HOSE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) for(hose = hose_head; hose; hose = hose->next)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (hose->index == bus) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (!hose) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /* Special hook for ISA access. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (bus == 0 && dfn == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) hose = pci_isa_hose;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) dev = pci_get_domain_bus_and_slot(0, bus, dfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) hose = dev->sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) pci_dev_put(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) switch (which & ~IOBASE_FROM_HOSE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) case IOBASE_HOSE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return hose->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) case IOBASE_SPARSE_MEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return hose->sparse_mem_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) case IOBASE_DENSE_MEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return hose->dense_mem_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) case IOBASE_SPARSE_IO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return hose->sparse_io_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) case IOBASE_DENSE_IO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return hose->dense_io_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) case IOBASE_ROOT_BUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return hose->bus->number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* Destroy an __iomem token. Not copied from lib/iomap.c. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) void pci_iounmap(struct pci_dev *dev, void __iomem * addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (__is_mmio(addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) iounmap(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) EXPORT_SYMBOL(pci_iounmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* FIXME: Some boxes have multiple ISA bridges! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) struct pci_dev *isa_bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) EXPORT_SYMBOL(isa_bridge);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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