^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/alpha/kernel/machvec_impl.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1997, 1998 Richard Henderson
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This file has goodies to help simplify instantiation of machine vectors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* Whee. These systems don't have an HAE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) IRONGATE, MARVEL, POLARIS, TSUNAMI, TITAN, WILDFIRE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) Fix things up for the GENERIC kernel by defining the HAE address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) to be that of the cache. Now we can read and write it as we like. ;-) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define IRONGATE_HAE_ADDRESS (&alpha_mv.hae_cache)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define MARVEL_HAE_ADDRESS (&alpha_mv.hae_cache)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define POLARIS_HAE_ADDRESS (&alpha_mv.hae_cache)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define TSUNAMI_HAE_ADDRESS (&alpha_mv.hae_cache)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define TITAN_HAE_ADDRESS (&alpha_mv.hae_cache)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define WILDFIRE_HAE_ADDRESS (&alpha_mv.hae_cache)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #ifdef CIA_ONE_HAE_WINDOW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CIA_HAE_ADDRESS (&alpha_mv.hae_cache)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #ifdef MCPCIA_ONE_HAE_WINDOW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MCPCIA_HAE_ADDRESS (&alpha_mv.hae_cache)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #ifdef T2_ONE_HAE_WINDOW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define T2_HAE_ADDRESS (&alpha_mv.hae_cache)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* Only a few systems don't define IACK_SC, handling all interrupts through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) the SRM console. But splitting out that one case from IO() below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) seems like such a pain. Define this to get things to compile. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define JENSEN_IACK_SC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define T2_IACK_SC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define WILDFIRE_IACK_SC 1 /* FIXME */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * Some helpful macros for filling in the blanks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CAT1(x,y) x##y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CAT(x,y) CAT1(x,y)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DO_DEFAULT_RTC .rtc_port = 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DO_EV4_MMU \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .max_asn = EV4_MAX_ASN, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .mv_switch_mm = ev4_switch_mm, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .mv_activate_mm = ev4_activate_mm, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .mv_flush_tlb_current = ev4_flush_tlb_current, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .mv_flush_tlb_current_page = ev4_flush_tlb_current_page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DO_EV5_MMU \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .max_asn = EV5_MAX_ASN, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .mv_switch_mm = ev5_switch_mm, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .mv_activate_mm = ev5_activate_mm, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .mv_flush_tlb_current = ev5_flush_tlb_current, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .mv_flush_tlb_current_page = ev5_flush_tlb_current_page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define DO_EV6_MMU \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .max_asn = EV6_MAX_ASN, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .mv_switch_mm = ev5_switch_mm, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .mv_activate_mm = ev5_activate_mm, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .mv_flush_tlb_current = ev5_flush_tlb_current, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .mv_flush_tlb_current_page = ev5_flush_tlb_current_page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DO_EV7_MMU \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .max_asn = EV6_MAX_ASN, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .mv_switch_mm = ev5_switch_mm, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .mv_activate_mm = ev5_activate_mm, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .mv_flush_tlb_current = ev5_flush_tlb_current, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .mv_flush_tlb_current_page = ev5_flush_tlb_current_page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define IO_LITE(UP,low) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .hae_register = (unsigned long *) CAT(UP,_HAE_ADDRESS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .iack_sc = CAT(UP,_IACK_SC), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .mv_ioread8 = CAT(low,_ioread8), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .mv_ioread16 = CAT(low,_ioread16), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .mv_ioread32 = CAT(low,_ioread32), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .mv_iowrite8 = CAT(low,_iowrite8), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .mv_iowrite16 = CAT(low,_iowrite16), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .mv_iowrite32 = CAT(low,_iowrite32), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .mv_readb = CAT(low,_readb), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .mv_readw = CAT(low,_readw), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .mv_readl = CAT(low,_readl), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .mv_readq = CAT(low,_readq), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .mv_writeb = CAT(low,_writeb), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .mv_writew = CAT(low,_writew), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .mv_writel = CAT(low,_writel), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .mv_writeq = CAT(low,_writeq), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .mv_ioportmap = CAT(low,_ioportmap), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .mv_ioremap = CAT(low,_ioremap), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .mv_iounmap = CAT(low,_iounmap), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .mv_is_ioaddr = CAT(low,_is_ioaddr), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .mv_is_mmio = CAT(low,_is_mmio) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define IO(UP,low) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) IO_LITE(UP,low), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .pci_ops = &CAT(low,_pci_ops), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .mv_pci_tbi = CAT(low,_pci_tbi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define DO_APECS_IO IO(APECS,apecs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define DO_CIA_IO IO(CIA,cia)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define DO_IRONGATE_IO IO(IRONGATE,irongate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define DO_LCA_IO IO(LCA,lca)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define DO_MARVEL_IO IO(MARVEL,marvel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define DO_MCPCIA_IO IO(MCPCIA,mcpcia)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define DO_POLARIS_IO IO(POLARIS,polaris)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define DO_T2_IO IO(T2,t2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define DO_TSUNAMI_IO IO(TSUNAMI,tsunami)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define DO_TITAN_IO IO(TITAN,titan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define DO_WILDFIRE_IO IO(WILDFIRE,wildfire)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define DO_PYXIS_IO IO_LITE(CIA,cia_bwx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .pci_ops = &cia_pci_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .mv_pci_tbi = cia_pci_tbi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * In a GENERIC kernel, we have lots of these vectors floating about,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * all but one of which we want to go away. In a non-GENERIC kernel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * we want only one, ever.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * Accomplish this in the GENERIC kernel by putting all of the vectors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * in the .init.data section where they'll go away. We'll copy the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * one we want to the real alpha_mv vector in setup_arch.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * Accomplish this in a non-GENERIC kernel by ifdef'ing out all but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * one of the vectors, which will not reside in .init.data. We then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * alias this one vector to alpha_mv, so no copy is needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * Upshot: set __initdata to nothing for non-GENERIC kernels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #ifdef CONFIG_ALPHA_GENERIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define __initmv __initdata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define ALIAS_MV(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define __initmv __refdata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* GCC actually has a syntax for defining aliases, but is under some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) delusion that you shouldn't be able to declare it extern somewhere
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) else beforehand. Fine. We'll do it ourselves. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define ALIAS_MV(system) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct alpha_machine_vector alpha_mv __attribute__((alias(#system "_mv"))); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) EXPORT_SYMBOL(alpha_mv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define ALIAS_MV(system) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) asm(".global alpha_mv\nalpha_mv = " #system "_mv"); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) EXPORT_SYMBOL(alpha_mv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #endif /* GENERIC */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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