^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Alpha specific irq code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel_stat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/machvec.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/perf_event.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/mce.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "proto.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "irq_impl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* Hack minimum IPL during interrupt processing for broken hardware. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #ifdef CONFIG_ALPHA_BROKEN_IRQ_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) int __min_ipl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) EXPORT_SYMBOL(__min_ipl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * Performance counter hook. A module can override this to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * do something useful.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) dummy_perf(unsigned long vector, struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) irq_err_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) printk(KERN_CRIT "Performance counter interrupt!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) void (*perf_irq)(unsigned long, struct pt_regs *) = dummy_perf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) EXPORT_SYMBOL(perf_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * The main interrupt entry point.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) asmlinkage void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) do_entInt(unsigned long type, unsigned long vector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) unsigned long la_ptr, struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct pt_regs *old_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * Disable interrupts during IRQ handling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * Note that there is no matching local_irq_enable() due to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * severe problems with RTI at IPL0 and some MILO PALcode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * (namely LX164).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) local_irq_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) handle_ipi(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) irq_err_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) printk(KERN_CRIT "Interprocessor interrupt? "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) "You must be kidding!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) old_regs = set_irq_regs(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) handle_irq(RTC_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) set_irq_regs(old_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) old_regs = set_irq_regs(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) alpha_mv.machine_check(vector, la_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) set_irq_regs(old_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) old_regs = set_irq_regs(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) alpha_mv.device_interrupt(vector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) set_irq_regs(old_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) perf_irq(la_ptr, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) printk(KERN_CRIT "Hardware intr %ld %lx? Huh?\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) type, vector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) printk(KERN_CRIT "PC = %016lx PS=%04lx\n", regs->pc, regs->ps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) common_init_isa_dma(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) outb(0, DMA1_RESET_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) outb(0, DMA2_RESET_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) outb(0, DMA1_CLR_MASK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) outb(0, DMA2_CLR_MASK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) init_IRQ(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* Just in case the platform init_irq() causes interrupts/mchecks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) (as is the case with RAWHIDE, at least). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) wrent(entInt, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) alpha_mv.init_irq();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * machine error checks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MCHK_K_TPERR 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MCHK_K_TCPERR 0x0082
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define MCHK_K_HERR 0x0084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MCHK_K_ECC_C 0x0086
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MCHK_K_ECC_NC 0x0088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MCHK_K_OS_BUGCHECK 0x008A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MCHK_K_PAL_BUGCHECK 0x0090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #ifndef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct mcheck_info __mcheck_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) process_mcheck_info(unsigned long vector, unsigned long la_ptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) const char *machine, int expected)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct el_common *mchk_header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) const char *reason;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * See if the machine check is due to a badaddr() and if so,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * ignore it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #ifdef CONFIG_VERBOSE_MCHECK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (alpha_verbose_mcheck > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) printk(KERN_CRIT "%s machine check %s\n", machine,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) expected ? "expected." : "NOT expected!!!");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (expected) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) int cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) mcheck_expected(cpu) = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) mcheck_taken(cpu) = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) mchk_header = (struct el_common *)la_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) printk(KERN_CRIT "%s machine check: vector=0x%lx pc=0x%lx code=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) machine, vector, get_irq_regs()->pc, mchk_header->code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) switch (mchk_header->code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* Machine check reasons. Defined according to PALcode sources. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) case 0x80: reason = "tag parity error"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) case 0x82: reason = "tag control parity error"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) case 0x84: reason = "generic hard error"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) case 0x86: reason = "correctable ECC error"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) case 0x88: reason = "uncorrectable ECC error"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) case 0x8A: reason = "OS-specific PAL bugcheck"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) case 0x90: reason = "callsys in kernel mode"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) case 0x96: reason = "i-cache read retryable error"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) case 0x98: reason = "processor detected hard error"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* System specific (these are for Alcor, at least): */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) case 0x202: reason = "system detected hard error"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) case 0x203: reason = "system detected uncorrectable ECC error"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) case 0x204: reason = "SIO SERR occurred on PCI bus"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) case 0x205: reason = "parity error detected by core logic"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) case 0x206: reason = "SIO IOCHK occurred on ISA bus"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) case 0x207: reason = "non-existent memory error"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) case 0x208: reason = "MCHK_K_DCSR"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) case 0x209: reason = "PCI SERR detected"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) case 0x20b: reason = "PCI data parity error detected"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) case 0x20d: reason = "PCI address parity error detected"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) case 0x20f: reason = "PCI master abort error"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) case 0x211: reason = "PCI target abort error"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) case 0x213: reason = "scatter/gather PTE invalid error"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) case 0x215: reason = "flash ROM write error"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) case 0x217: reason = "IOA timeout detected"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) case 0x219: reason = "IOCHK#, EISA add-in board parity or other catastrophic error"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) case 0x21b: reason = "EISA fail-safe timer timeout"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) case 0x21d: reason = "EISA bus time-out"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) case 0x21f: reason = "EISA software generated NMI"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) case 0x221: reason = "unexpected ev5 IRQ[3] interrupt"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) default: reason = "unknown"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) printk(KERN_CRIT "machine check type: %s%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) reason, mchk_header->retry ? " (retryable)" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) dik_show_regs(get_irq_regs(), NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #ifdef CONFIG_VERBOSE_MCHECK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (alpha_verbose_mcheck > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* Dump the logout area to give all info. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) unsigned long *ptr = (unsigned long *)la_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) long i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) for (i = 0; i < mchk_header->size / sizeof(long); i += 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) printk(KERN_CRIT " +%8lx %016lx %016lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) i*sizeof(long), ptr[i], ptr[i+1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #endif /* CONFIG_VERBOSE_MCHECK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * The special RTC interrupt type. The interrupt itself was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * processed by PALcode, and comes in via entInt vector 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) init_rtc_irq(irq_handler_t handler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) irq_set_chip_and_handler_name(RTC_IRQ, &dummy_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) handle_percpu_irq, "RTC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (!handler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) handler = rtc_timer_interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (request_irq(RTC_IRQ, handler, 0, "timer", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) pr_err("Failed to register timer interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }