Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *	linux/arch/alpha/kernel/es1888.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Init the built-in ES1888 sound chip (SB16 compatible)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "proto.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) es1888_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	/* Sequence of IO reads to init the audio controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	inb(0x0229);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	inb(0x0229);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	inb(0x0229);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	inb(0x022b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	inb(0x0229);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	inb(0x022b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	inb(0x0229);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	inb(0x0229);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	inb(0x022b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	inb(0x0229);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	inb(0x0220); /* This sets the base address to 0x220 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	/* Sequence to set DMA channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	outb(0x01, 0x0226);		/* reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	inb(0x0226);			/* pause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	outb(0x00, 0x0226);		/* release reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	while (!(inb(0x022e) & 0x80))	/* wait for bit 7 to assert*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	inb(0x022a);			/* pause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	outb(0xc6, 0x022c);		/* enable extended mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	inb(0x022a);			/* pause, also forces the write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	while (inb(0x022c) & 0x80)	/* wait for bit 7 to deassert */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	outb(0xb1, 0x022c);		/* setup for write to Interrupt CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	while (inb(0x022c) & 0x80)	/* wait for bit 7 to deassert */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	outb(0x14, 0x022c);		/* set IRQ 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	while (inb(0x022c) & 0x80)	/* wait for bit 7 to deassert */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	outb(0xb2, 0x022c);		/* setup for write to DMA CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	while (inb(0x022c) & 0x80)	/* wait for bit 7 to deassert */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	outb(0x18, 0x022c);		/* set DMA channel 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	inb(0x022c);			/* force the write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }