^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/alpha/kernel/err_titan.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2000 Jeff Wiedemeier (Compaq Computer Corporation)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Error handling code supporting TITAN systems
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/core_titan.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/hwrpb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/err_common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/err_ev6.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/irq_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "err_impl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "proto.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) titan_parse_c_misc(u64 c_misc, int print)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #ifdef CONFIG_VERBOSE_MCHECK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) char *src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) int nxs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) int status = MCHK_DISPOSITION_REPORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TITAN__CCHIP_MISC__NXM (1UL << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TITAN__CCHIP_MISC__NXS__S (29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TITAN__CCHIP_MISC__NXS__M (0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) if (!(c_misc & TITAN__CCHIP_MISC__NXM))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) return MCHK_DISPOSITION_UNKNOWN_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #ifdef CONFIG_VERBOSE_MCHECK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) if (!print)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) nxs = EXTRACT(c_misc, TITAN__CCHIP_MISC__NXS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) switch(nxs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) case 0: /* CPU 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) case 1: /* CPU 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) case 2: /* CPU 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) case 3: /* CPU 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) src = "CPU";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* num is already the CPU number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) case 4: /* Pchip 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) case 5: /* Pchip 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) src = "Pchip";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) nxs -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) default:/* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) src = "Unknown, NXS =";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* leave num untouched */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) printk("%s Non-existent memory access from: %s %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) err_print_prefix, src, nxs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #endif /* CONFIG_VERBOSE_MCHECK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) titan_parse_p_serror(int which, u64 serror, int print)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) int status = MCHK_DISPOSITION_REPORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #ifdef CONFIG_VERBOSE_MCHECK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static const char * const serror_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) "GPCI", "APCI", "AGP HP", "AGP LP"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static const char * const serror_cmd[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) "DMA Read", "DMA RMW", "SGTE Read", "Reserved"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #endif /* CONFIG_VERBOSE_MCHECK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define TITAN__PCHIP_SERROR__LOST_UECC (1UL << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define TITAN__PCHIP_SERROR__UECC (1UL << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define TITAN__PCHIP_SERROR__CRE (1UL << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define TITAN__PCHIP_SERROR__NXIO (1UL << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define TITAN__PCHIP_SERROR__LOST_CRE (1UL << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define TITAN__PCHIP_SERROR__ECCMASK (TITAN__PCHIP_SERROR__UECC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) TITAN__PCHIP_SERROR__CRE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define TITAN__PCHIP_SERROR__ERRMASK (TITAN__PCHIP_SERROR__LOST_UECC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) TITAN__PCHIP_SERROR__UECC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) TITAN__PCHIP_SERROR__CRE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) TITAN__PCHIP_SERROR__NXIO | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) TITAN__PCHIP_SERROR__LOST_CRE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define TITAN__PCHIP_SERROR__SRC__S (52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define TITAN__PCHIP_SERROR__SRC__M (0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define TITAN__PCHIP_SERROR__CMD__S (54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define TITAN__PCHIP_SERROR__CMD__M (0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define TITAN__PCHIP_SERROR__SYN__S (56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define TITAN__PCHIP_SERROR__SYN__M (0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define TITAN__PCHIP_SERROR__ADDR__S (15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define TITAN__PCHIP_SERROR__ADDR__M (0xffffffffUL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (!(serror & TITAN__PCHIP_SERROR__ERRMASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return MCHK_DISPOSITION_UNKNOWN_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #ifdef CONFIG_VERBOSE_MCHECK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (!print)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) printk("%s PChip %d SERROR: %016llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) err_print_prefix, which, serror);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (serror & TITAN__PCHIP_SERROR__ECCMASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) printk("%s %sorrectable ECC Error:\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) " Source: %-6s Command: %-8s Syndrome: 0x%08x\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) " Address: 0x%llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) err_print_prefix,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) (serror & TITAN__PCHIP_SERROR__UECC) ? "Unc" : "C",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) serror_src[EXTRACT(serror, TITAN__PCHIP_SERROR__SRC)],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) serror_cmd[EXTRACT(serror, TITAN__PCHIP_SERROR__CMD)],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) (unsigned)EXTRACT(serror, TITAN__PCHIP_SERROR__SYN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) EXTRACT(serror, TITAN__PCHIP_SERROR__ADDR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (serror & TITAN__PCHIP_SERROR__NXIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) printk("%s Non Existent I/O Error\n", err_print_prefix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (serror & TITAN__PCHIP_SERROR__LOST_UECC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) printk("%s Lost Uncorrectable ECC Error\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) err_print_prefix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (serror & TITAN__PCHIP_SERROR__LOST_CRE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) printk("%s Lost Correctable ECC Error\n", err_print_prefix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #endif /* CONFIG_VERBOSE_MCHECK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) titan_parse_p_perror(int which, int port, u64 perror, int print)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) int cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) unsigned long addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) int status = MCHK_DISPOSITION_REPORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #ifdef CONFIG_VERBOSE_MCHECK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static const char * const perror_cmd[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) "Interrupt Acknowledge", "Special Cycle",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) "I/O Read", "I/O Write",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) "Reserved", "Reserved",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) "Memory Read", "Memory Write",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) "Reserved", "Reserved",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) "Configuration Read", "Configuration Write",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) "Memory Read Multiple", "Dual Address Cycle",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) "Memory Read Line", "Memory Write and Invalidate"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #endif /* CONFIG_VERBOSE_MCHECK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define TITAN__PCHIP_PERROR__LOST (1UL << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define TITAN__PCHIP_PERROR__SERR (1UL << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define TITAN__PCHIP_PERROR__PERR (1UL << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define TITAN__PCHIP_PERROR__DCRTO (1UL << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define TITAN__PCHIP_PERROR__SGE (1UL << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define TITAN__PCHIP_PERROR__APE (1UL << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define TITAN__PCHIP_PERROR__TA (1UL << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define TITAN__PCHIP_PERROR__DPE (1UL << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define TITAN__PCHIP_PERROR__NDS (1UL << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define TITAN__PCHIP_PERROR__IPTPR (1UL << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define TITAN__PCHIP_PERROR__IPTPW (1UL << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define TITAN__PCHIP_PERROR__ERRMASK (TITAN__PCHIP_PERROR__LOST | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) TITAN__PCHIP_PERROR__SERR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) TITAN__PCHIP_PERROR__PERR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) TITAN__PCHIP_PERROR__DCRTO | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) TITAN__PCHIP_PERROR__SGE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) TITAN__PCHIP_PERROR__APE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) TITAN__PCHIP_PERROR__TA | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) TITAN__PCHIP_PERROR__DPE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) TITAN__PCHIP_PERROR__NDS | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) TITAN__PCHIP_PERROR__IPTPR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) TITAN__PCHIP_PERROR__IPTPW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define TITAN__PCHIP_PERROR__DAC (1UL << 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define TITAN__PCHIP_PERROR__MWIN (1UL << 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define TITAN__PCHIP_PERROR__CMD__S (52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define TITAN__PCHIP_PERROR__CMD__M (0x0f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define TITAN__PCHIP_PERROR__ADDR__S (14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define TITAN__PCHIP_PERROR__ADDR__M (0x1fffffffful)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (!(perror & TITAN__PCHIP_PERROR__ERRMASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return MCHK_DISPOSITION_UNKNOWN_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) cmd = EXTRACT(perror, TITAN__PCHIP_PERROR__CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) addr = EXTRACT(perror, TITAN__PCHIP_PERROR__ADDR) << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * Initializing the BIOS on a video card on a bus without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * a south bridge (subtractive decode agent) can result in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * master aborts as the BIOS probes the capabilities of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * card. XFree86 does such initialization. If the error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * is a master abort (No DevSel as PCI Master) and the command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * is an I/O read or write below the address where we start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * assigning PCI I/O spaces (SRM uses 0x1000), then mark the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * error as dismissable so starting XFree86 doesn't result
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * in a series of uncorrectable errors being reported. Also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * dismiss master aborts to VGA frame buffer space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * (0xA0000 - 0xC0000) and legacy BIOS space (0xC0000 - 0x100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * for the same reason.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * Also mark the error dismissible if it looks like the right
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * error but only the Lost bit is set. Since the BIOS initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * can cause multiple master aborts and the error interrupt can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * be handled on a different CPU than the BIOS code is run on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * it is possible for a second master abort to occur between the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * time the PALcode reads PERROR and the time it writes PERROR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * to acknowledge the error. If this timing happens, a second
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * error will be signalled after the first, and if no additional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * errors occur, will look like a Lost error with no additional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * errors on the same transaction as the previous error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (((perror & TITAN__PCHIP_PERROR__NDS) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ((perror & TITAN__PCHIP_PERROR__ERRMASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) TITAN__PCHIP_PERROR__LOST)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) ((((cmd & 0xE) == 2) && (addr < 0x1000)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) (((cmd & 0xE) == 6) && (addr >= 0xA0000) && (addr < 0x100000)))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) status = MCHK_DISPOSITION_DISMISS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #ifdef CONFIG_VERBOSE_MCHECK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (!print)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) printk("%s PChip %d %cPERROR: %016llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) err_print_prefix, which,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) port ? 'A' : 'G', perror);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (perror & TITAN__PCHIP_PERROR__IPTPW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) printk("%s Invalid Peer-to-Peer Write\n", err_print_prefix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (perror & TITAN__PCHIP_PERROR__IPTPR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) printk("%s Invalid Peer-to-Peer Read\n", err_print_prefix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (perror & TITAN__PCHIP_PERROR__NDS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) printk("%s No DEVSEL as PCI Master [Master Abort]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) err_print_prefix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (perror & TITAN__PCHIP_PERROR__DPE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) printk("%s Data Parity Error\n", err_print_prefix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (perror & TITAN__PCHIP_PERROR__TA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) printk("%s Target Abort\n", err_print_prefix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (perror & TITAN__PCHIP_PERROR__APE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) printk("%s Address Parity Error\n", err_print_prefix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (perror & TITAN__PCHIP_PERROR__SGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) printk("%s Scatter-Gather Error, Invalid PTE\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) err_print_prefix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (perror & TITAN__PCHIP_PERROR__DCRTO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) printk("%s Delayed-Completion Retry Timeout\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) err_print_prefix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (perror & TITAN__PCHIP_PERROR__PERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) printk("%s PERR Asserted\n", err_print_prefix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (perror & TITAN__PCHIP_PERROR__SERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) printk("%s SERR Asserted\n", err_print_prefix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (perror & TITAN__PCHIP_PERROR__LOST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) printk("%s Lost Error\n", err_print_prefix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) printk("%s Command: 0x%x - %s\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) " Address: 0x%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) err_print_prefix,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) cmd, perror_cmd[cmd],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (perror & TITAN__PCHIP_PERROR__DAC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) printk("%s Dual Address Cycle\n", err_print_prefix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (perror & TITAN__PCHIP_PERROR__MWIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) printk("%s Hit in Monster Window\n", err_print_prefix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #endif /* CONFIG_VERBOSE_MCHECK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) titan_parse_p_agperror(int which, u64 agperror, int print)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) int status = MCHK_DISPOSITION_REPORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #ifdef CONFIG_VERBOSE_MCHECK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) int cmd, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) unsigned long addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static const char * const agperror_cmd[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) "Read (low-priority)", "Read (high-priority)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) "Write (low-priority)", "Write (high-priority)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) "Reserved", "Reserved",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) "Flush", "Fence"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #endif /* CONFIG_VERBOSE_MCHECK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define TITAN__PCHIP_AGPERROR__LOST (1UL << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define TITAN__PCHIP_AGPERROR__LPQFULL (1UL << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define TITAN__PCHIP_AGPERROR__HPQFULL (1UL << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define TITAN__PCHIP_AGPERROR__RESCMD (1UL << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define TITAN__PCHIP_AGPERROR__IPTE (1UL << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define TITAN__PCHIP_AGPERROR__PTP (1UL << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define TITAN__PCHIP_AGPERROR__NOWINDOW (1UL << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define TITAN__PCHIP_AGPERROR__ERRMASK (TITAN__PCHIP_AGPERROR__LOST | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) TITAN__PCHIP_AGPERROR__LPQFULL | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) TITAN__PCHIP_AGPERROR__HPQFULL | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) TITAN__PCHIP_AGPERROR__RESCMD | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) TITAN__PCHIP_AGPERROR__IPTE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) TITAN__PCHIP_AGPERROR__PTP | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) TITAN__PCHIP_AGPERROR__NOWINDOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define TITAN__PCHIP_AGPERROR__DAC (1UL << 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define TITAN__PCHIP_AGPERROR__MWIN (1UL << 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define TITAN__PCHIP_AGPERROR__FENCE (1UL << 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define TITAN__PCHIP_AGPERROR__CMD__S (50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define TITAN__PCHIP_AGPERROR__CMD__M (0x07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define TITAN__PCHIP_AGPERROR__ADDR__S (15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define TITAN__PCHIP_AGPERROR__ADDR__M (0xffffffffUL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define TITAN__PCHIP_AGPERROR__LEN__S (53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define TITAN__PCHIP_AGPERROR__LEN__M (0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (!(agperror & TITAN__PCHIP_AGPERROR__ERRMASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return MCHK_DISPOSITION_UNKNOWN_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #ifdef CONFIG_VERBOSE_MCHECK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (!print)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) cmd = EXTRACT(agperror, TITAN__PCHIP_AGPERROR__CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) addr = EXTRACT(agperror, TITAN__PCHIP_AGPERROR__ADDR) << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) len = EXTRACT(agperror, TITAN__PCHIP_AGPERROR__LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) printk("%s PChip %d AGPERROR: %016llx\n", err_print_prefix,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) which, agperror);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (agperror & TITAN__PCHIP_AGPERROR__NOWINDOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) printk("%s No Window\n", err_print_prefix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (agperror & TITAN__PCHIP_AGPERROR__PTP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) printk("%s Peer-to-Peer set\n", err_print_prefix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (agperror & TITAN__PCHIP_AGPERROR__IPTE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) printk("%s Invalid PTE\n", err_print_prefix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (agperror & TITAN__PCHIP_AGPERROR__RESCMD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) printk("%s Reserved Command\n", err_print_prefix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (agperror & TITAN__PCHIP_AGPERROR__HPQFULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) printk("%s HP Transaction Received while Queue Full\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) err_print_prefix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (agperror & TITAN__PCHIP_AGPERROR__LPQFULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) printk("%s LP Transaction Received while Queue Full\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) err_print_prefix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (agperror & TITAN__PCHIP_AGPERROR__LOST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) printk("%s Lost Error\n", err_print_prefix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) printk("%s Command: 0x%x - %s, %d Quadwords%s\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) " Address: 0x%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) err_print_prefix, cmd, agperror_cmd[cmd], len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) (agperror & TITAN__PCHIP_AGPERROR__FENCE) ? ", FENCE" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (agperror & TITAN__PCHIP_AGPERROR__DAC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) printk("%s Dual Address Cycle\n", err_print_prefix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (agperror & TITAN__PCHIP_AGPERROR__MWIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) printk("%s Hit in Monster Window\n", err_print_prefix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #endif /* CONFIG_VERBOSE_MCHECK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) titan_parse_p_chip(int which, u64 serror, u64 gperror,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) u64 aperror, u64 agperror, int print)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) int status = MCHK_DISPOSITION_UNKNOWN_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) status |= titan_parse_p_serror(which, serror, print);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) status |= titan_parse_p_perror(which, 0, gperror, print);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) status |= titan_parse_p_perror(which, 1, aperror, print);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) status |= titan_parse_p_agperror(which, agperror, print);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) titan_process_logout_frame(struct el_common *mchk_header, int print)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct el_TITAN_sysdata_mcheck *tmchk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) (struct el_TITAN_sysdata_mcheck *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) ((unsigned long)mchk_header + mchk_header->sys_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) int status = MCHK_DISPOSITION_UNKNOWN_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) status |= titan_parse_c_misc(tmchk->c_misc, print);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) status |= titan_parse_p_chip(0, tmchk->p0_serror, tmchk->p0_gperror,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) tmchk->p0_aperror, tmchk->p0_agperror,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) print);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) status |= titan_parse_p_chip(1, tmchk->p1_serror, tmchk->p1_gperror,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) tmchk->p1_aperror, tmchk->p1_agperror,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) print);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) titan_machine_check(unsigned long vector, unsigned long la_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct el_common *mchk_header = (struct el_common *)la_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct el_TITAN_sysdata_mcheck *tmchk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) (struct el_TITAN_sysdata_mcheck *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ((unsigned long)mchk_header + mchk_header->sys_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) u64 irqmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * Mask of Titan interrupt sources which are reported as machine checks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * 63 - CChip Error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * 62 - PChip 0 H_Error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * 61 - PChip 1 H_Error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * 60 - PChip 0 C_Error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * 59 - PChip 1 C_Error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define TITAN_MCHECK_INTERRUPT_MASK 0xF800000000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * Sync the processor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) draina();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * Only handle system errors here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if ((vector != SCB_Q_SYSMCHK) && (vector != SCB_Q_SYSERR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) ev6_machine_check(vector, la_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * It's a system error, handle it here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) * The PALcode has already cleared the error, so just parse it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * Parse the logout frame without printing first. If the only error(s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * found are classified as "dismissable", then just dismiss them and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * don't print any message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (titan_process_logout_frame(mchk_header, 0) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) MCHK_DISPOSITION_DISMISS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) char *saved_err_prefix = err_print_prefix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) err_print_prefix = KERN_CRIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * Either a nondismissable error was detected or no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * recognized error was detected in the logout frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * -- report the error in either case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) printk("%s"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) "*System %s Error (Vector 0x%x) reported on CPU %d:\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) err_print_prefix,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) (vector == SCB_Q_SYSERR)?"Correctable":"Uncorrectable",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) (unsigned int)vector, (int)smp_processor_id());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #ifdef CONFIG_VERBOSE_MCHECK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) titan_process_logout_frame(mchk_header, alpha_verbose_mcheck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (alpha_verbose_mcheck)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) dik_show_regs(get_irq_regs(), NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #endif /* CONFIG_VERBOSE_MCHECK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) err_print_prefix = saved_err_prefix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * Convert any pending interrupts which report as system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * machine checks to interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) irqmask = tmchk->c_dirx & TITAN_MCHECK_INTERRUPT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) titan_dispatch_irqs(irqmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) * Release the logout frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) wrmces(0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * Subpacket Annotations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static char *el_titan_pchip0_extended_annotation[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) "Subpacket Header", "P0_SCTL", "P0_SERREN",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) "P0_APCTL", "P0_APERREN", "P0_AGPERREN",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) "P0_ASPRST", "P0_AWSBA0", "P0_AWSBA1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) "P0_AWSBA2", "P0_AWSBA3", "P0_AWSM0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) "P0_AWSM1", "P0_AWSM2", "P0_AWSM3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) "P0_ATBA0", "P0_ATBA1", "P0_ATBA2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) "P0_ATBA3", "P0_GPCTL", "P0_GPERREN",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) "P0_GSPRST", "P0_GWSBA0", "P0_GWSBA1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) "P0_GWSBA2", "P0_GWSBA3", "P0_GWSM0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) "P0_GWSM1", "P0_GWSM2", "P0_GWSM3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) "P0_GTBA0", "P0_GTBA1", "P0_GTBA2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) "P0_GTBA3", NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static char *el_titan_pchip1_extended_annotation[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) "Subpacket Header", "P1_SCTL", "P1_SERREN",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) "P1_APCTL", "P1_APERREN", "P1_AGPERREN",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) "P1_ASPRST", "P1_AWSBA0", "P1_AWSBA1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) "P1_AWSBA2", "P1_AWSBA3", "P1_AWSM0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) "P1_AWSM1", "P1_AWSM2", "P1_AWSM3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) "P1_ATBA0", "P1_ATBA1", "P1_ATBA2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) "P1_ATBA3", "P1_GPCTL", "P1_GPERREN",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) "P1_GSPRST", "P1_GWSBA0", "P1_GWSBA1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) "P1_GWSBA2", "P1_GWSBA3", "P1_GWSM0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) "P1_GWSM1", "P1_GWSM2", "P1_GWSM3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) "P1_GTBA0", "P1_GTBA1", "P1_GTBA2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) "P1_GTBA3", NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static char *el_titan_memory_extended_annotation[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) "Subpacket Header", "AAR0", "AAR1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) "AAR2", "AAR3", "P0_SCTL",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) "P0_GPCTL", "P0_APCTL", "P1_SCTL",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) "P1_GPCTL", "P1_SCTL", NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static struct el_subpacket_annotation el_titan_annotations[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) SUBPACKET_ANNOTATION(EL_CLASS__REGATTA_FAMILY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) EL_TYPE__REGATTA__TITAN_PCHIP0_EXTENDED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) "Titan PChip 0 Extended Frame",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) el_titan_pchip0_extended_annotation),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) SUBPACKET_ANNOTATION(EL_CLASS__REGATTA_FAMILY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) EL_TYPE__REGATTA__TITAN_PCHIP1_EXTENDED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) "Titan PChip 1 Extended Frame",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) el_titan_pchip1_extended_annotation),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) SUBPACKET_ANNOTATION(EL_CLASS__REGATTA_FAMILY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) EL_TYPE__REGATTA__TITAN_MEMORY_EXTENDED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) "Titan Memory Extended Frame",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) el_titan_memory_extended_annotation),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) SUBPACKET_ANNOTATION(EL_CLASS__REGATTA_FAMILY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) EL_TYPE__TERMINATION__TERMINATION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) "Termination Subpacket",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static struct el_subpacket *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) el_process_regatta_subpacket(struct el_subpacket *header)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (header->class != EL_CLASS__REGATTA_FAMILY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) printk("%s ** Unexpected header CLASS %d TYPE %d, aborting\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) err_print_prefix,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) header->class, header->type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) switch(header->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) case EL_TYPE__REGATTA__PROCESSOR_ERROR_FRAME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) case EL_TYPE__REGATTA__SYSTEM_ERROR_FRAME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) case EL_TYPE__REGATTA__ENVIRONMENTAL_FRAME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) case EL_TYPE__REGATTA__PROCESSOR_DBL_ERROR_HALT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) case EL_TYPE__REGATTA__SYSTEM_DBL_ERROR_HALT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) printk("%s ** Occurred on CPU %d:\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) err_print_prefix,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) (int)header->by_type.regatta_frame.cpuid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) privateer_process_logout_frame((struct el_common *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) header->by_type.regatta_frame.data_start, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) printk("%s ** REGATTA TYPE %d SUBPACKET\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) err_print_prefix, header->type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) el_annotate_subpacket(header);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return (struct el_subpacket *)((unsigned long)header + header->length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static struct el_subpacket_handler titan_subpacket_handler =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) SUBPACKET_HANDLER_INIT(EL_CLASS__REGATTA_FAMILY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) el_process_regatta_subpacket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) titan_register_error_handlers(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) size_t i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) for (i = 0; i < ARRAY_SIZE (el_titan_annotations); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) cdl_register_subpacket_annotation(&el_titan_annotations[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) cdl_register_subpacket_handler(&titan_subpacket_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) ev6_register_error_handlers();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) * Privateer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) privateer_process_680_frame(struct el_common *mchk_header, int print)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) int status = MCHK_DISPOSITION_UNKNOWN_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #ifdef CONFIG_VERBOSE_MCHECK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) struct el_PRIVATEER_envdata_mcheck *emchk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) (struct el_PRIVATEER_envdata_mcheck *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) ((unsigned long)mchk_header + mchk_header->sys_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /* TODO - categorize errors, for now, no error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (!print)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /* TODO - decode instead of just dumping... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) printk("%s Summary Flags: %016llx\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) " CChip DIRx: %016llx\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) " System Management IR: %016llx\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) " CPU IR: %016llx\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) " Power Supply IR: %016llx\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) " LM78 Fault Status: %016llx\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) " System Doors: %016llx\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) " Temperature Warning: %016llx\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) " Fan Control: %016llx\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) " Fatal Power Down Code: %016llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) err_print_prefix,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) emchk->summary,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) emchk->c_dirx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) emchk->smir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) emchk->cpuir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) emchk->psir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) emchk->fault,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) emchk->sys_doors,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) emchk->temp_warn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) emchk->fan_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) emchk->code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #endif /* CONFIG_VERBOSE_MCHECK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) privateer_process_logout_frame(struct el_common *mchk_header, int print)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) struct el_common_EV6_mcheck *ev6mchk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) (struct el_common_EV6_mcheck *)mchk_header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) int status = MCHK_DISPOSITION_UNKNOWN_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) * Machine check codes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #define PRIVATEER_MCHK__CORR_ECC 0x86 /* 630 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define PRIVATEER_MCHK__DC_TAG_PERR 0x9E /* 630 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define PRIVATEER_MCHK__PAL_BUGCHECK 0x8E /* 670 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #define PRIVATEER_MCHK__OS_BUGCHECK 0x90 /* 670 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #define PRIVATEER_MCHK__PROC_HRD_ERR 0x98 /* 670 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define PRIVATEER_MCHK__ISTREAM_CMOV_PRX 0xA0 /* 670 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define PRIVATEER_MCHK__ISTREAM_CMOV_FLT 0xA2 /* 670 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #define PRIVATEER_MCHK__SYS_HRD_ERR 0x202 /* 660 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #define PRIVATEER_MCHK__SYS_CORR_ERR 0x204 /* 620 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define PRIVATEER_MCHK__SYS_ENVIRON 0x206 /* 680 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) switch(ev6mchk->MCHK_Code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) * Vector 630 - Processor, Correctable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) case PRIVATEER_MCHK__CORR_ECC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) case PRIVATEER_MCHK__DC_TAG_PERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) * Fall through to vector 670 for processing...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) * Vector 670 - Processor, Uncorrectable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) case PRIVATEER_MCHK__PAL_BUGCHECK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) case PRIVATEER_MCHK__OS_BUGCHECK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) case PRIVATEER_MCHK__PROC_HRD_ERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) case PRIVATEER_MCHK__ISTREAM_CMOV_PRX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) case PRIVATEER_MCHK__ISTREAM_CMOV_FLT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) status |= ev6_process_logout_frame(mchk_header, print);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) * Vector 620 - System, Correctable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) case PRIVATEER_MCHK__SYS_CORR_ERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) * Fall through to vector 660 for processing...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) * Vector 660 - System, Uncorrectable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) case PRIVATEER_MCHK__SYS_HRD_ERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) status |= titan_process_logout_frame(mchk_header, print);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) * Vector 680 - System, Environmental
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) case PRIVATEER_MCHK__SYS_ENVIRON: /* System, Environmental */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) status |= privateer_process_680_frame(mchk_header, print);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) * Unknown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) status |= MCHK_DISPOSITION_REPORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (print) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) printk("%s** Unknown Error, frame follows\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) err_print_prefix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) mchk_dump_logout_frame(mchk_header);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) privateer_machine_check(unsigned long vector, unsigned long la_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) struct el_common *mchk_header = (struct el_common *)la_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) struct el_TITAN_sysdata_mcheck *tmchk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) (struct el_TITAN_sysdata_mcheck *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) (la_ptr + mchk_header->sys_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) u64 irqmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) char *saved_err_prefix = err_print_prefix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #define PRIVATEER_680_INTERRUPT_MASK (0xE00UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #define PRIVATEER_HOTPLUG_INTERRUPT_MASK (0xE00UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) * Sync the processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) draina();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) * Only handle system events here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (vector != SCB_Q_SYSEVENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) return titan_machine_check(vector, la_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) * Report the event - System Events should be reported even if no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) * error is indicated since the event could indicate the return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) * to normal status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) err_print_prefix = KERN_CRIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) printk("%s*System Event (Vector 0x%x) reported on CPU %d:\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) err_print_prefix,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) (unsigned int)vector, (int)smp_processor_id());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) privateer_process_680_frame(mchk_header, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) err_print_prefix = saved_err_prefix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) * Convert any pending interrupts which report as 680 machine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) * checks to interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) irqmask = tmchk->c_dirx & PRIVATEER_680_INTERRUPT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) * Dispatch the interrupt(s).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) titan_dispatch_irqs(irqmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) * Release the logout frame.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) wrmces(0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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