Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Definitions for use with the Alpha wrperfmon PAL call.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef __ALPHA_WRPERFMON_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define __ALPHA_WRPERFMON_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) /* Following commands are implemented on all CPUs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define PERFMON_CMD_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define PERFMON_CMD_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define PERFMON_CMD_DESIRED_EVENTS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define PERFMON_CMD_LOGGING_OPTIONS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* Following commands on EV5/EV56/PCA56 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define PERFMON_CMD_INT_FREQ 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PERFMON_CMD_ENABLE_CLEAR 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* Following commands are on EV5 and better CPUs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PERFMON_CMD_READ 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PERFMON_CMD_WRITE 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* Following command are on EV6 and better CPUs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PERFMON_CMD_ENABLE_WRITE 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* Following command are on EV67 and better CPUs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PERFMON_CMD_I_STAT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PERFMON_CMD_PMPC 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* EV5/EV56/PCA56 Counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define EV5_PCTR_0 (1UL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define EV5_PCTR_1 (1UL<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define EV5_PCTR_2 (1UL<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define EV5_PCTR_0_COUNT_SHIFT 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define EV5_PCTR_1_COUNT_SHIFT 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define EV5_PCTR_2_COUNT_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define EV5_PCTR_0_COUNT_MASK 0xffffUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define EV5_PCTR_1_COUNT_MASK 0xffffUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define EV5_PCTR_2_COUNT_MASK 0x3fffUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* EV6 Counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define EV6_PCTR_0 (1UL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define EV6_PCTR_1 (1UL<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define EV6_PCTR_0_COUNT_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define EV6_PCTR_1_COUNT_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define EV6_PCTR_0_COUNT_MASK 0xfffffUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define EV6_PCTR_1_COUNT_MASK 0xfffffUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* EV67 (and subsequent) counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define EV67_PCTR_0 (1UL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define EV67_PCTR_1 (1UL<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define EV67_PCTR_0_COUNT_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define EV67_PCTR_1_COUNT_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define EV67_PCTR_0_COUNT_MASK 0xfffffUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define EV67_PCTR_1_COUNT_MASK 0xfffffUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)  * The Alpha Architecure Handbook, vers. 4 (1998) appears to have a misprint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)  *  in Table E-23 regarding the bits that set the event PCTR 1 counts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)  *  Hopefully what we have here is correct.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define EV6_PCTR_0_EVENT_MASK 0x10UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define EV6_PCTR_1_EVENT_MASK 0x0fUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* EV6 Events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define EV6_PCTR_0_CYCLES (0UL << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define EV6_PCTR_0_INSTRUCTIONS (1UL << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define EV6_PCTR_1_CYCLES 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define EV6_PCTR_1_BRANCHES 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define EV6_PCTR_1_BRANCH_MISPREDICTS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define EV6_PCTR_1_DTB_SINGLE_MISSES 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define EV6_PCTR_1_DTB_DOUBLE_MISSES 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define EV6_PCTR_1_ITB_MISSES 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define EV6_PCTR_1_UNALIGNED_TRAPS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define EV6_PCTR_1_REPLY_TRAPS 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* From the Alpha Architecture Reference Manual, 4th edn., 2002 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define EV67_PCTR_MODE_MASK 0x10UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define EV67_PCTR_EVENT_MASK 0x0CUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define EV67_PCTR_MODE_PROFILEME (1UL<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define EV67_PCTR_MODE_AGGREGATE (0UL<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define EV67_PCTR_INSTR_CYCLES (0UL<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define EV67_PCTR_CYCLES_UNDEF (1UL<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define EV67_PCTR_INSTR_BCACHEMISS (2UL<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define EV67_PCTR_CYCLES_MBOX (3UL<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #endif