Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *	Access to VGA videoram
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *	(c) 1998 Martin Mares <mj@ucw.cz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #ifndef _LINUX_ASM_VGA_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define _LINUX_ASM_VGA_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define VT_BUF_HAVE_RW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define VT_BUF_HAVE_MEMSETW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define VT_BUF_HAVE_MEMCPYW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) static inline void scr_writew(u16 val, volatile u16 *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	if (__is_ioaddr(addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 		__raw_writew(val, (volatile u16 __iomem *) addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 		*addr = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static inline u16 scr_readw(volatile const u16 *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	if (__is_ioaddr(addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		return __raw_readw((volatile const u16 __iomem *) addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		return *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static inline void scr_memsetw(u16 *s, u16 c, unsigned int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	if (__is_ioaddr(s))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		memsetw_io((u16 __iomem *) s, c, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		memset16(s, c, count / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* Do not trust that the usage will be correct; analyze the arguments.  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) extern void scr_memcpyw(u16 *d, const u16 *s, unsigned int count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* ??? These are currently only used for downloading character sets.  As
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)    such, they don't need memory barriers.  Is this all they are intended
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)    to be used for?  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define vga_readb(a)	readb((u8 __iomem *)(a))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define vga_writeb(v,a)	writeb(v, (u8 __iomem *)(a))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #ifdef CONFIG_VGA_HOSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) extern struct pci_controller *pci_vga_hose;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) # define __is_port_vga(a)       \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	(((a) >= 0x3b0) && ((a) < 0x3e0) && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	 ((a) != 0x3b3) && ((a) != 0x3d3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) # define __is_mem_vga(a) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	(((a) >= 0xa0000) && ((a) <= 0xc0000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) # define FIXUP_IOADDR_VGA(a) do {                       \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	if (pci_vga_hose && __is_port_vga(a))     \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 		(a) += pci_vga_hose->io_space->start;	  \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)  } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) # define FIXUP_MEMADDR_VGA(a) do {                       \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	if (pci_vga_hose && __is_mem_vga(a))     \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 		(a) += pci_vga_hose->mem_space->start; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)  } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #else /* CONFIG_VGA_HOSE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) # define pci_vga_hose 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) # define __is_port_vga(a) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) # define __is_mem_vga(a) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) # define FIXUP_IOADDR_VGA(a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) # define FIXUP_MEMADDR_VGA(a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #endif /* CONFIG_VGA_HOSE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define VGA_MAP_MEM(x,s)	((unsigned long) ioremap(x, s))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #endif