^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef _ALPHA_SPINLOCK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define _ALPHA_SPINLOCK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <asm/current.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <asm/barrier.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <asm/processor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Simple spin lock operations. There are two variants, one clears IRQ's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * on the local processor, one does not.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * We make no fairness assumptions. They have a cost.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define arch_spin_is_locked(x) ((x)->lock != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) static inline int arch_spin_value_unlocked(arch_spinlock_t lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) return lock.lock == 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static inline void arch_spin_unlock(arch_spinlock_t * lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) lock->lock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static inline void arch_spin_lock(arch_spinlock_t * lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) long tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) __asm__ __volatile__(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) "1: ldl_l %0,%1\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) " bne %0,2f\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) " lda %0,1\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) " stl_c %0,%1\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) " beq %0,2f\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) " mb\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) ".subsection 2\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) "2: ldl %0,%1\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) " bne %0,2b\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) " br 1b\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) ".previous"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) : "=&r" (tmp), "=m" (lock->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) : "m"(lock->lock) : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static inline int arch_spin_trylock(arch_spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return !test_and_set_bit(0, &lock->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /***********************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static inline void arch_read_lock(arch_rwlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) long regx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) __asm__ __volatile__(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) "1: ldl_l %1,%0\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) " blbs %1,6f\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) " subl %1,2,%1\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) " stl_c %1,%0\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) " beq %1,6f\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) " mb\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) ".subsection 2\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) "6: ldl %1,%0\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) " blbs %1,6b\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) " br 1b\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) ".previous"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) : "=m" (*lock), "=&r" (regx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) : "m" (*lock) : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static inline void arch_write_lock(arch_rwlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) long regx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) __asm__ __volatile__(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) "1: ldl_l %1,%0\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) " bne %1,6f\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) " lda %1,1\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) " stl_c %1,%0\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) " beq %1,6f\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) " mb\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ".subsection 2\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) "6: ldl %1,%0\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) " bne %1,6b\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) " br 1b\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) ".previous"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) : "=m" (*lock), "=&r" (regx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) : "m" (*lock) : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static inline int arch_read_trylock(arch_rwlock_t * lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) long regx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) int success;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) __asm__ __volatile__(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) "1: ldl_l %1,%0\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) " lda %2,0\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) " blbs %1,2f\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) " subl %1,2,%2\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) " stl_c %2,%0\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) " beq %2,6f\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) "2: mb\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ".subsection 2\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) "6: br 1b\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) ".previous"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) : "=m" (*lock), "=&r" (regx), "=&r" (success)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) : "m" (*lock) : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return success;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static inline int arch_write_trylock(arch_rwlock_t * lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) long regx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) int success;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) __asm__ __volatile__(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) "1: ldl_l %1,%0\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) " lda %2,0\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) " bne %1,2f\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) " lda %2,1\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) " stl_c %2,%0\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) " beq %2,6f\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) "2: mb\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) ".subsection 2\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) "6: br 1b\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) ".previous"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) : "=m" (*lock), "=&r" (regx), "=&r" (success)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) : "m" (*lock) : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return success;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static inline void arch_read_unlock(arch_rwlock_t * lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) long regx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) __asm__ __volatile__(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) " mb\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) "1: ldl_l %1,%0\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) " addl %1,2,%1\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) " stl_c %1,%0\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) " beq %1,6f\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) ".subsection 2\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) "6: br 1b\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) ".previous"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) : "=m" (*lock), "=&r" (regx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) : "m" (*lock) : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static inline void arch_write_unlock(arch_rwlock_t * lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) lock->lock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #endif /* _ALPHA_SPINLOCK_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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