^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef _ALPHA_PGTABLE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define _ALPHA_PGTABLE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <asm-generic/pgtable-nopud.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This file contains the functions and defines necessary to modify and use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * the Alpha page table tree.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * This hopefully works with any standard Alpha page-size, as defined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * in <asm/page.h> (currently 8192).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mmzone.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/processor.h> /* For TASK_SIZE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/machvec.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/setup.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct mm_struct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct vm_area_struct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* Certain architectures need to do special things when PTEs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * within a page table are directly modified. Thus, the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * hook is made available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define set_pte(pteptr, pteval) ((*(pteptr)) = (pteval))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* PMD_SHIFT determines the size of the area a second-level page table can map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PMD_SIZE (1UL << PMD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PMD_MASK (~(PMD_SIZE-1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* PGDIR_SHIFT determines what a third-level page table entry can map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PGDIR_SHIFT (PAGE_SHIFT + 2*(PAGE_SHIFT-3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PGDIR_MASK (~(PGDIR_SIZE-1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * Entries per page directory level: the Alpha is three-level, with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * all levels having a one-page page table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PTRS_PER_PTE (1UL << (PAGE_SHIFT-3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PTRS_PER_PMD (1UL << (PAGE_SHIFT-3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PTRS_PER_PGD (1UL << (PAGE_SHIFT-3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define FIRST_USER_ADDRESS 0UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* Number of pointers that fit on a page: this will go away. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PTRS_PER_PAGE (1UL << (PAGE_SHIFT-3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #ifdef CONFIG_ALPHA_LARGE_VMALLOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define VMALLOC_START 0xfffffe0000000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define VMALLOC_START (-2*PGDIR_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define VMALLOC_END (-PGDIR_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * OSF/1 PAL-code-imposed page table bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define _PAGE_VALID 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define _PAGE_FOR 0x0002 /* used for page protection (fault on read) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define _PAGE_FOW 0x0004 /* used for page protection (fault on write) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define _PAGE_FOE 0x0008 /* used for page protection (fault on exec) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define _PAGE_ASM 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define _PAGE_KRE 0x0100 /* xxx - see below on the "accessed" bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define _PAGE_URE 0x0200 /* xxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define _PAGE_KWE 0x1000 /* used to do the dirty bit in software */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define _PAGE_UWE 0x2000 /* used to do the dirty bit in software */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* .. and these are ours ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define _PAGE_DIRTY 0x20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define _PAGE_ACCESSED 0x40000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * NOTE! The "accessed" bit isn't necessarily exact: it can be kept exactly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * by software (use the KRE/URE/KWE/UWE bits appropriately), but I'll fake it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * Under Linux/AXP, the "accessed" bit just means "read", and I'll just use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * the KRE/URE bits to watch for it. That way we don't need to overload the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * KWE/UWE bits with both handling dirty and accessed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * Note that the kernel uses the accessed bit just to check whether to page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * out a page or not, so it doesn't have to be exact anyway.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define __DIRTY_BITS (_PAGE_DIRTY | _PAGE_KWE | _PAGE_UWE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define __ACCESS_BITS (_PAGE_ACCESSED | _PAGE_KRE | _PAGE_URE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define _PFN_MASK 0xFFFFFFFF00000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define _PAGE_TABLE (_PAGE_VALID | __DIRTY_BITS | __ACCESS_BITS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define _PAGE_CHG_MASK (_PFN_MASK | __DIRTY_BITS | __ACCESS_BITS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * All the normal masks have the "page accessed" bits on, as any time they are used,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * the page is accessed. They are cleared only by the page-out routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PAGE_NONE __pgprot(_PAGE_VALID | __ACCESS_BITS | _PAGE_FOR | _PAGE_FOW | _PAGE_FOE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define PAGE_SHARED __pgprot(_PAGE_VALID | __ACCESS_BITS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PAGE_COPY __pgprot(_PAGE_VALID | __ACCESS_BITS | _PAGE_FOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define PAGE_READONLY __pgprot(_PAGE_VALID | __ACCESS_BITS | _PAGE_FOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define PAGE_KERNEL __pgprot(_PAGE_VALID | _PAGE_ASM | _PAGE_KRE | _PAGE_KWE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define _PAGE_NORMAL(x) __pgprot(_PAGE_VALID | __ACCESS_BITS | (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define _PAGE_P(x) _PAGE_NORMAL((x) | (((x) & _PAGE_FOW)?0:_PAGE_FOW))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define _PAGE_S(x) _PAGE_NORMAL(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * The hardware can handle write-only mappings, but as the Alpha
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * architecture does byte-wide writes with a read-modify-write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * sequence, it's not practical to have write-without-read privs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * Thus the "-w- -> rw-" and "-wx -> rwx" mapping here (and in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * arch/alpha/mm/fault.c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* xwr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define __P000 _PAGE_P(_PAGE_FOE | _PAGE_FOW | _PAGE_FOR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define __P001 _PAGE_P(_PAGE_FOE | _PAGE_FOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define __P010 _PAGE_P(_PAGE_FOE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define __P011 _PAGE_P(_PAGE_FOE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define __P100 _PAGE_P(_PAGE_FOW | _PAGE_FOR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define __P101 _PAGE_P(_PAGE_FOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define __P110 _PAGE_P(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define __P111 _PAGE_P(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define __S000 _PAGE_S(_PAGE_FOE | _PAGE_FOW | _PAGE_FOR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define __S001 _PAGE_S(_PAGE_FOE | _PAGE_FOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define __S010 _PAGE_S(_PAGE_FOE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define __S011 _PAGE_S(_PAGE_FOE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define __S100 _PAGE_S(_PAGE_FOW | _PAGE_FOR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define __S101 _PAGE_S(_PAGE_FOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define __S110 _PAGE_S(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define __S111 _PAGE_S(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * pgprot_noncached() is only for infiniband pci support, and a real
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * implementation for RAM would be more complicated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define pgprot_noncached(prot) (prot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * BAD_PAGETABLE is used when we need a bogus page-table, while
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * BAD_PAGE is used for a bogus page.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * ZERO_PAGE is a global shared page that is always zero: used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * for zero-mapped memory areas etc..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) extern pte_t __bad_page(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) extern pmd_t * __bad_pagetable(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) extern unsigned long __zero_page(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define BAD_PAGETABLE __bad_pagetable()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define BAD_PAGE __bad_page()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define ZERO_PAGE(vaddr) (virt_to_page(ZERO_PGE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* number of bits that fit into a memory pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define BITS_PER_PTR (8*sizeof(unsigned long))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* to align the pointer to a pointer address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define PTR_MASK (~(sizeof(void*)-1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* sizeof(void*)==1<<SIZEOF_PTR_LOG2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define SIZEOF_PTR_LOG2 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* to find an entry in a page-table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define PAGE_PTR(address) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ((unsigned long)(address)>>(PAGE_SHIFT-SIZEOF_PTR_LOG2)&PTR_MASK&~PAGE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * On certain platforms whose physical address space can overlap KSEG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * namely EV6 and above, we must re-twiddle the physaddr to restore the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * correct high-order bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * This is extremely confusing until you realize that this is actually
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * just working around a userspace bug. The X server was intending to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * provide the physical address but instead provided the KSEG address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * Or tried to, except it's not representable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * On Tsunami there's nothing meaningful at 0x40000000000, so this is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * a safe thing to do. Come the first core logic that does put something
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * in this area -- memory or whathaveyou -- then this hack will have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * to go away. So be prepared!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #if defined(CONFIG_ALPHA_GENERIC) && defined(USE_48_BIT_KSEG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #error "EV6-only feature in a generic kernel"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #if defined(CONFIG_ALPHA_GENERIC) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) (defined(CONFIG_ALPHA_EV6) && !defined(USE_48_BIT_KSEG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define KSEG_PFN (0xc0000000000UL >> PAGE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define PHYS_TWIDDLE(pfn) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) ((((pfn) & KSEG_PFN) == (0x40000000000UL >> PAGE_SHIFT)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) ? ((pfn) ^= KSEG_PFN) : (pfn))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define PHYS_TWIDDLE(pfn) (pfn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * Conversion functions: convert a page and protection to a page entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * and a page entry and page directory to the page they refer to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #ifndef CONFIG_DISCONTIGMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define page_to_pa(page) (((page) - mem_map) << PAGE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define pte_pfn(pte) (pte_val(pte) >> 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define pte_page(pte) pfn_to_page(pte_pfn(pte))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define mk_pte(page, pgprot) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) ({ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) pte_t pte; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) pte_val(pte) = (page_to_pfn(page) << 32) | pgprot_val(pgprot); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) pte; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) extern inline pte_t pfn_pte(unsigned long physpfn, pgprot_t pgprot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) { pte_t pte; pte_val(pte) = (PHYS_TWIDDLE(physpfn) << 32) | pgprot_val(pgprot); return pte; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) extern inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) { pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) extern inline void pmd_set(pmd_t * pmdp, pte_t * ptep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) { pmd_val(*pmdp) = _PAGE_TABLE | ((((unsigned long) ptep) - PAGE_OFFSET) << (32-PAGE_SHIFT)); }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) extern inline void pud_set(pud_t * pudp, pmd_t * pmdp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) { pud_val(*pudp) = _PAGE_TABLE | ((((unsigned long) pmdp) - PAGE_OFFSET) << (32-PAGE_SHIFT)); }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) extern inline unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) pmd_page_vaddr(pmd_t pmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return ((pmd_val(pmd) & _PFN_MASK) >> (32-PAGE_SHIFT)) + PAGE_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #ifndef CONFIG_DISCONTIGMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define pmd_page(pmd) (mem_map + ((pmd_val(pmd) & _PFN_MASK) >> 32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define pud_page(pud) (mem_map + ((pud_val(pud) & _PFN_MASK) >> 32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) extern inline unsigned long pud_page_vaddr(pud_t pgd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) { return PAGE_OFFSET + ((pud_val(pgd) & _PFN_MASK) >> (32-PAGE_SHIFT)); }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) extern inline int pte_none(pte_t pte) { return !pte_val(pte); }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) extern inline int pte_present(pte_t pte) { return pte_val(pte) & _PAGE_VALID; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) extern inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) pte_val(*ptep) = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) extern inline int pmd_none(pmd_t pmd) { return !pmd_val(pmd); }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) extern inline int pmd_bad(pmd_t pmd) { return (pmd_val(pmd) & ~_PFN_MASK) != _PAGE_TABLE; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) extern inline int pmd_present(pmd_t pmd) { return pmd_val(pmd) & _PAGE_VALID; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) extern inline void pmd_clear(pmd_t * pmdp) { pmd_val(*pmdp) = 0; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) extern inline int pud_none(pud_t pud) { return !pud_val(pud); }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) extern inline int pud_bad(pud_t pud) { return (pud_val(pud) & ~_PFN_MASK) != _PAGE_TABLE; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) extern inline int pud_present(pud_t pud) { return pud_val(pud) & _PAGE_VALID; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) extern inline void pud_clear(pud_t * pudp) { pud_val(*pudp) = 0; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * The following only work if pte_present() is true.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * Undefined behaviour if not..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) extern inline int pte_write(pte_t pte) { return !(pte_val(pte) & _PAGE_FOW); }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) extern inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) extern inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) extern inline pte_t pte_wrprotect(pte_t pte) { pte_val(pte) |= _PAGE_FOW; return pte; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) extern inline pte_t pte_mkclean(pte_t pte) { pte_val(pte) &= ~(__DIRTY_BITS); return pte; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) extern inline pte_t pte_mkold(pte_t pte) { pte_val(pte) &= ~(__ACCESS_BITS); return pte; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) extern inline pte_t pte_mkwrite(pte_t pte) { pte_val(pte) &= ~_PAGE_FOW; return pte; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) extern inline pte_t pte_mkdirty(pte_t pte) { pte_val(pte) |= __DIRTY_BITS; return pte; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) extern inline pte_t pte_mkyoung(pte_t pte) { pte_val(pte) |= __ACCESS_BITS; return pte; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * The smp_rmb() in the following functions are required to order the load of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * *dir (the pointer in the top level page table) with any subsequent load of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * the returned pmd_t *ret (ret is data dependent on *dir).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * If this ordering is not enforced, the CPU might load an older value of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * *ret, which may be uninitialized data. See mm/memory.c:__pte_alloc for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * Note that we never change the mm->pgd pointer after the task is running, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * pgd_offset does not require such a barrier.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* Find an entry in the second-level page table.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) extern inline pmd_t * pmd_offset(pud_t * dir, unsigned long address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) pmd_t *ret = (pmd_t *) pud_page_vaddr(*dir) + ((address >> PMD_SHIFT) & (PTRS_PER_PAGE - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) smp_rmb(); /* see above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define pmd_offset pmd_offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* Find an entry in the third-level page table.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) extern inline pte_t * pte_offset_kernel(pmd_t * dir, unsigned long address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) pte_t *ret = (pte_t *) pmd_page_vaddr(*dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) + ((address >> PAGE_SHIFT) & (PTRS_PER_PAGE - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) smp_rmb(); /* see above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define pte_offset_kernel pte_offset_kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) extern pgd_t swapper_pg_dir[1024];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * The Alpha doesn't have any external MMU info: the kernel page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * tables contain all the necessary information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) extern inline void update_mmu_cache(struct vm_area_struct * vma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) unsigned long address, pte_t *ptep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * Non-present pages: high 24 bits are offset, next 8 bits type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * low 32 bits zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) extern inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) { pte_t pte; pte_val(pte) = (type << 32) | (offset << 40); return pte; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define __swp_type(x) (((x).val >> 32) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define __swp_offset(x) ((x).val >> 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define __swp_entry(type, off) ((swp_entry_t) { pte_val(mk_swap_pte((type), (off))) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define __swp_entry_to_pte(x) ((pte_t) { (x).val })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #ifndef CONFIG_DISCONTIGMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define kern_addr_valid(addr) (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define pte_ERROR(e) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define pmd_ERROR(e) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define pgd_ERROR(e) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) extern void paging_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /* We have our own get_unmapped_area to cope with ADDR_LIMIT_32BIT. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define HAVE_ARCH_UNMAPPED_AREA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #endif /* _ALPHA_PGTABLE_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags