^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Machine dependent access functions for RTC registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #ifndef __ASM_ALPHA_MC146818RTC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define __ASM_ALPHA_MC146818RTC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef RTC_PORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define RTC_PORT(x) (0x70 + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define RTC_ALWAYS_BCD 1 /* RTC operates in binary mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * The yet supported machines all access the RTC index register via
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * an ISA port access but the way to access the date register differs ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CMOS_READ(addr) ({ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) outb_p((addr),RTC_PORT(0)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) inb_p(RTC_PORT(1)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CMOS_WRITE(val, addr) ({ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) outb_p((addr),RTC_PORT(0)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) outb_p((val),RTC_PORT(1)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #endif /* __ASM_ALPHA_MC146818RTC_H */